KiCad constraints / design rules errors

i am fairly new to pcb design and so far everything went well. However now i have a problem with KiCads constraints/design-rules (i hope this is the right category)

After trying to import JLCPCBs manufacturing capabilities i noticed that my usb-c receptacle does not comply with these rules, which results in an error in the DRC. I have already tried looking for other peoples design rules using this standard connector. However when I import them to KiCad most of their values are just set to 0. What part of JLCPCBs or KiCads rules do I misunderstand?
As far as I can see all of JLCPCBs rules dont really apply to my problem.

Thank you for your help!

Here is the missing photo since i can only post one per post:

Copper to hole is really about how well the drills get registered + their expected variance. If you are willing to accept a NPTH that slightly overlaps your copper, then just set it to 0. JLCPCB doesn’t directly state how well registered their holes are. But you could roughly extrapolate from the via-to-via clearance.

It looks like you are choosing the different net clearance, which is not what the hole clearance is about. This is just a physical distance for the actual hole.

For PTH, the electrical clearance for the inner plating is checked separately (this is what different net checks are usually about)

Also, I always like to note for people that JLCPCB explicitly does NOT support KiCad (we’ve asked) or the KiCad community. There are multiple vendors that do, including Aisler, OSHPark, PCBWay and HQ NextPCB. When you order from vendors that support KiCad, you are helping to make KiCad better and the KiCad community stronger. And this doesn’t need to cost you anything.

For example:

Hello and welcome @schnabulator

Here is a link to the FAQ article explaining the forum use to new members.

All the FAQs are are available via the link at the top RH side of every forum page.

You need to read another 14 posts for at least 5 minutes total, to be promoted to “Basic”; after which there are no posting limitations. :slightly_smiling_face:

There is a JLC PCB fabrication plugin object for Ki,

I have not tried it.
The issue with Ki is it has 15 settings in DRC, and JLC has like 50 different settings
PCB Manufacturing & Assembly Capabilities - JLCPCB.
I imported a clean Eagle project (different issue) and got lots of errors. Eagle has almost enough settings (60 ish) but there are many it does not cover, like treatment of vias, (four choices), back-drilling whatnot, which must be included as separate information.
I have ordered hundreds of boards from them with extremely few issues.
I’d like to resolve this issue and start using Ki.