I see references in this category that some are using Kicad for DDR3 and DDR4 but from my understanding the technical ability for time matching the package delays doesn’t exist yet? What are people using for say ARM board designs? I’ve been doing CAD for about 35 years and still have some of my Z80 chips that were fun to do back in the day but static ram was easy then and I had not kept up. I had mostly been doing Microchip and other various controller boards but now need to make an ARM PCB with DDR3/4, eMMC and a little work with the PCI bus however I am a little hesitant thinking Kicad is not up to this task so correct me if I am wrong there.
If the feature does not exist then wondering if it is being worked on or if I need to find a different EDA for this particular PCB need?
Each DDR4 package line has a different timing and lining all those up so the source and destination timings are within tolerance seems a bit tricky. It would appear other EDA take care of this for you with their high speed design features but several have referencing in forum posts this functionality does not exist in Kicad which I’m not aware of as true or false other than I just want to make sure I’m designing it in an EDA that can test or verify my DDR is going to work correctly and not use guess work.
It is a RK3568 with a Micro 512x32 chip design. From what I read every memory chip can have different package delays requiring different routing to get the DDR timing to be with in tolerance otherwise if it takes 3 pico seconds for a specific data line to be right that could be really bad.
I never found an example of any rockchip designs or any ARM open source designs using Kicad for what its worth so I wasn’t even sure if anyone had tried this.
my experience with DDR3 is: the FPGA manufacturer gives You some length matching specifications, and You route it according it. if You have timing tolerances, then i would let a tx-line tool calculate the length tolerances, and route according them.
That makes sense. I will reference this video at 18:30 https://www.youtube.com/watch?v=5vPeSdU22ns&t=703s as it specifies one pin with a delay of 41 and another at 61ps so just need to do the data line on either pin to make the balance of the time I take it.
Please note the status showing the “pad to die length”, “routed length” and “full length”.
Keeping the length equal can be as well seen when you open the Inspect\Net Inspector.
If you group the signals in a spreadsheet too you will see the length of the various traces… in my case I see:
KiCAD is very much ready for DDR3/4 design.
Antmicro Ltd has such designs put up on their GitHub:
Just clone it and have a look.
They have a few other designs published too:
The workflow is roughly like follows (sorry if I get something wrong, I have done this last time in KiCad V6 days and something might have changed) - you do this on a controlled-impedance PCB:
You can calculate the right track sizes with Saturn PCB Toolkit – Saturn PCB or similar calculator (some PCB fabs even offer such calculators on their websites).
Then you create some net-classes for each of the impedances you need (like USB 3.0, PCI-e and so on; I think you can use the same net-class as long as the inter-pair and pair-ground plane (differential and single-ended) impedances stay the same.
Insert the track parameters calculated in Step 1 in net-class deffinition for diff-pair traces. (This is best done already on the SCH design stage if you go SCH->PCB, but you can ofc do it later).
Route them minding the length displayed on the bottom. You can then use the serpentining (skew-adjustment) tools and so on to fine-tune the length.
Since we can assume the speed of the signal propagation is constant when the impedance of the traces is constant (you do want such a design to be on an impedance-controlled PCB), time matching is done by track length matching.
Yes so before I do the DDR4 project I’m working on a NXP IMX6UL DDR3L project and will see how that goes. The development costs are much cheaper if I have to do it a few times.
And yes, its a lot of work getting it clean, equal in length, checking the capabilities of your chip to equalise bits… and so on.
Thank you for your enlightening post! I have this question: I know there is a special footprint file format both Altera and Xilinx (whatever their names du jour are now) use. Can KiCAD make use of these files? Does the information in these files include pad-to-die delays?
I do not know of such a tool in KiCAD… thinking about it I would say: Oh yes, having a CSV file with the parameters in tabs for each FPGA/CPU bank would be wonderfull. And then being able for each pin to add name, position in the symbol, add a symbol type, a position on foot print, add the pad to die length, and so on, would make my life simpler. The way I do it is similar and a more pragmatic approach: I use the Xilinx Vivado to generate a pin report file. Search in the Xilinx user forum for “Package Signal Delay Information”. There you will find the complete discussion. Or here a short instruction: Make a simple Vivado project, do the implementation, open the implementation, go to File/“Export I/O ports” and select the CSV format… which in turn allows me to see the time of flight between pad and die called “Min Trace Delay (ps)” and “Max Trace Delay (ps)”, the name and pin as a table as shown in this excerp.
IO Bank
Pin Number
Site
Site Type
Min Trace Delay (ps)
Max Trace Delay (ps)
Prohibit
Interface
Signal Name
Direction
DiffPair Type
DiffPair Signal
IO Standard
Drive (mA)
Slew Rate
OUTPUT_IMPEDANCE
PRE_EMPHASIS
LVDS_PRE_EMPHASIS
EQUALIZATION
Pull Type
DQS_BIAS
DIFF_TERM_ADV
OFFCHIP_TERM
Board Signal
Board Voltage
ODT
504
W28
PS8_X0Y0
PS_DDR_A0_504
64.83
65.481
DDR4_A0
OUT
DDR4
34
RTT_NONE
504
AA25
PS8_X0Y0
PS_DDR_A10_504
73.445
74.183
DDR4_A10
OUT
DDR4
34
RTT_NONE
504
AA26
PS8_X0Y0
PS_DDR_A11_504
66.236
66.902
DDR4_A11
OUT
DDR4
34
RTT_NONE
504
AB25
PS8_X0Y0
PS_DDR_A12_504
78.9
79.693
DDR4_A12
OUT
DDR4
34
RTT_NONE
Then I calculate for my PCB material (with help of the epsilon r and speed of light) the equivalent trace length. In a table calculation software (EXCEL, LibreOffice, and so on) I calculate the pin location on the symbol and add it to my table before I generate the banks as shown in my example.
My pragnatic approach look messy but is way less work than adding each of the several hundred pins one by one.
the GPAC2_SOM layout seems suboptimal for high-speed signals. if there is GND around the fast lines, it needs correct distance from to line to form a coplanar waveguide. and the GND polygon should have via connections to the next GND plane at every corner.
how did You decide the spacing to the GND polygon?
