The coupling happen by the plane below and above the trace… basically forming a stripline. The coupling to the sides is very low and the reason for the GND plane is solely acting as a filler. Since I wondered if I’m able to simulate the PCB in ADS and see the effects of impedance mismatch and coupling I made the following:
So I checked that with KiCAD I’m able to do an EM simulation in ADS (not a big surprise since I’m using simply the Gerber files). Please note: Since this whole project was to learn the edges and interfaces of KiCAD, I used a 16 layer board!.. hence I have space for GND planes like you never have in a purely commercial product. In such complex, dense and comercial projects the EM simulation is very important… or at least an engineer with some experience and a long record of working boards
However, what I wanted to point out in my posts, was the possibility to have length equalization and the on chip flight time in the length equalization… not necessary a perfect, cheap, comercial board.
i know, its a bit idiotic to critic this PCB. but really dont think, that it has the intended impedance
Your signal has about 1GHz and i think the line is < 3cm what would mean its shorter then ʎ/10 and electrical small.
for the gap, my feeling says, its to small, but i dont really know.
to see the effect of the GND filling i would simulate S-parameter to 30GHz
A similar problem appeared when developing an FPGA from another manufacturer. The most important thing is to correctly configure the design rules. They depend not only on the simulator but also on the capabilities of production. The possible problems that I had were ideal operation in the simulator but the inability to manufacture such a board by production. Production means not only a piece of textolite in 10-20 layers with minimal gaps but also the direct installation of parts. At high frequencies it is advisable to use a special material such as Rogers or similar which has a constant wave resistance. When simulating with a regular FR-4, problems are possible, but this depends on the specific device.
Well, it is diffucult to argue against feelings. I set up the traces according the manufacturer abilities and based on the KiCAD calculator tool, I get ~30 Ohm impedance for the traces and then I simulated the PCB with ADS… just to have an estimation of what will most likely happen. Concerning the link length… yes, it is very short, as you see in the tables above, since I was able to fit all 5 DRAMS (64bit + 8 ECC) next to my MPSoC.
I fear your comment is a bit off topic, since we disussed here the trace length including the On Chip Fligh Time and length equalization for DDR 3/4 SDRAM done in KiCAD and not the PCB production and board setup. However, I see in your comment and the comments of oli_snr that this is something you would like to discuss, since it has to do with signal integrity and you see the trace length equalization including the On Chip Flight time related to DDR 3/4 SDRAM designs. Good, unless a moderator tell us to open another thread, let’s do some information exchange.
Yes Mihail, I agree with almost all of your points. It is common sense to: 1. Set up your PCB according to the ability of your manufacturer, 2. choose the right material and dimensions for the targeted frequency and 3. make sure the production is properly done.
Concerning 1: The board setup has to reflect the ability of the company. We evaluate companies with a pilote project, checking their ability and reproducability of their work. In addition the quality of the tools is evaluated, to see if the measurements are close to the predicted results. In simulation you may consider as well the production tolerances. For example what happens, if the trace impedance is off by lets say 10 %… the simulation may give you a hint what then will happen to your PCB. A wonderful source of information are the videos of Eric Bogatin… simply brilliant. I have in my company RF engineers doing mainly RF designs but they do as well checking of other people designs. Tools like Siemens HyperLynx need as well some experience to interprete and set up correctly… the same is true for Qucs and QucsStudio which oli_snr mentioned. The advantage of such tools is that companies sometimes give you models of their chips that you can simulate your design before you produce the PCB (IBIS or SPICE models for examples)… this is as well possible to some extent in KiCAD/NGSPICE.
Concerning 2: You proposed Rogers… well our experience with this family of PCB materials is that they are quite good concerning the RF properties but have usually mechanical limitations. We use the Rogers for RFFE electronics combined with FR4 for low speed part of the PCB. High speed digital PCBs using Megtron 6 or Isola materials. In Xilinx IBERT we usually inspect the eye diagram to see if the signal eye is wide and open. With this tool you may observe as well distortion of your signal, due to vias, impedance mismatch, coupling and so on.
Concerning 3: You may consider making a simple board implementing striplines or microstrips and check the impedance, tolerances and quality of the PCB manufacturer. This may give you an impression what to expect for your product, based on the comparison between calculation and estimations you made.
Your signal has about 1GHz and i think the line is < 3cm what would mean its shorter then ʎ/10 and electrical small.
In digital design, what matters is not the clock frequency but the edge rates (rise and fall times). The 10% rule of thumb applies to the rise and fall time: If it takes more than 10% of the rise or fall time for the pulse to travel from transmitter to receiver, then distributed techniques should be applied. You may have one pulse per hour but with very fast edges (in terms of circuit dimensions and propagation speed); you can mess up one pulse per hour as easily as i pulse per ns. In the RF/microwave world, you usually have channel bandwidth only a small percentage of the carrier frequency, so then speaking in terms of frequency and corresponding wavelength makes sense. From another point of view, the faster the rise/fall times, the wider the frequency content is, so yes, you need to know the pulse (wave) propagation properties to high frequencies. In the old days, Tek oscilloscope manuals gave the formula bandwidth = 0.35/risetime. In practice, that depends on the actual amplifiers. Wide s-parameter sweeps are necessary in the case of fast rise/fall times because dielectrics are dispersive, as they have to be (you may look up the Kramers-Kronig relationship in wikipedia for more information).
Yes, i was not writing about the clock fundamental freq but about the clock and its harmonics… i totally agree with You.
the circuits i work with in the “RF/microwave world” are typical DC…10GHz. so i wouldnt say its really that different from fast digital signals. only problems with dispersion could be different. but i would expect problem only in electric very long transmission-lines.
