Kicad and DDR4

Layout
21

@oli_snr

The coupling happen by the plane below and above the trace… basically forming a stripline. The coupling to the sides is very low and the reason for the GND plane is solely as filler. Since I wondered if I were able to simulate the PCB in ADS and see the effects of impedance mismatch and coupling I made the following:

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So I checked that with KiCAD I’m able to do an EM simulation in ADS (not a big surprise since I’m using simply the Gerber files). Please note: Since this whole project was to learn the edges and interfaces of KiCAD I used a 16 layer board!.. hence I have space for GND planes like you never have in a purely commercial product. In such projects the EM simulation is very important… or at least an engineer with some experience and a long record of working boards :slight_smile:
However, what I wanted to point out in my posts was the possibility to have length equalization and the on chip flight time in the length equalization… not necessary a perfect, cheap comercial board.

Cheers
Goran

22

i know, its a bit idiotic to critic this PCB. but really dont think, that it has the intended impedance :slight_smile:
Your signal has about 1GHz and i think the line is < 3cm what would mean its shorter then ʎ/10 and electrical small.

for the gap, my feeling says, its to small, but i dont really know.

to see the effect of the GND filling i would simulate S-parameter to 30GHz