(changed the topic from Schematic to Layout as it is having issues in Layout as well, and they are more important)
Hi all,
So I noticed that with KiCAD 9 when creating a new netclass in the Schematic editor it no longer adds the default values, this also carries over into the Layout editor where there are again no default values.
Is this intended or a bug?
(I had added the default values in the schematic editor for Single, JTAG & LVDS manually)
Also finding a couple of weird issues with PCB Layout now.
Custom rules are not overriding the set values in the Net Class.
It shows at the bottom of the screen that it is:
However it will not route the Differential pair until I set the âLVDSâ Net Class Differential Pair Gap to 0.15mm, or the Default Net Class Differential Pair Gap to 0.15mm.
Also weirdly if I set the âLVDSâ Net Class to 0.25mm and the Default Class to 0.15mm it also works.
If I set both to 0.25 mm it again will not start routing.
Just to add some clarification, the routing will start with the correct gap and track width as defined in my custom rules, but if I stop routing and then go back and try and start routing again that is when it fails to continue routing.
It seems to be that my custom rule will override the Net Class values only if my custom rule value is higher than the Net Class value. As setting the gap to 0.35mm works ok.
The empty values is expected behaviour. See the docs for the changes in v9:
That explains why they no longer have default values at creation, as they will default to Default if missing.
It doesnât explain why my custom rule on DP gap is only valid when starting a route from the pads, but then if I try to continue the route it is only allowed when either the Default of LVDS or the Default class is less than that set by the custom rule.
For example if DP gap is 0.25 mm in the Default class and I set a custom rule for an LVDS class as 0.15mm it will not allow me to continue the route, if I set the LVDS class to 0.25 or higher it has no issues.
Can you share the project, and exact steps which show the issue?
I canât share the actual project, but I have created a very simple project which shows the issue.
Diff_Pair_Gap.zip (9.4 KB)
This only has two connectors and one differential pair between them.
There are only the Default netclass and the LVDS netclass.
There is a custom rule that sets the Differential_Pair_Gap to 0.15mm, you can start the route at either connector and it will complete with no issues, however if you left click during the route it will stop at that point and no longer be able to continue routing.
If you then add a value of 0.15mm or less into the LVDS netclass DP Gap value it will be able to continue routing. Same if you just change the Default netclass DP Gap value to 0.15mm or less.
Weirdly if you set either to 0.15mm and the other to greater than 0.15mm it also can continue routing.
Just to add it also stops you routing a single track from either of the differential pair tracks until you edit the DP Gap value to 0.15mm or less, if you have already partly routed the pair.
Ah, I think whatâs happening here is that the router is intially ignoring the clearance constraint (which in the example project is 0.2mm), but when starting routing the next segment this constraint is then enforced.
If you reduce the Default netclass clearance to 0.15mm it works fine. I think the bug here is the initial routing being allowed, rather than the continuing routing not working.
So the values in the net classes override the custom rules, but only in one direction?
Also there isnât a priority in how the value is applied between the LVDS or the Default net class, you set either to 0.15mm it allows the custom rule.
So I set the Default to 0.15mm, the LVDS class to 0.2mm and the custom rule to 0.25mm, routing starts as expected at 0.25mm gap, and can be resumed with no issues. However I can then select each individual track and move it so they are 0.15mm apart. (same happens if you swap the LVDS and Default values)
This means that the custom rule is only applied when routing, after which it just obeys the Default class and ignores the LVDS class and the custom rule?
EDIT:
Just noticed you mentioned the clearance constraint, changing that to 0.15 mm does make it work, again regardless of what either net class has its DP Gap set to. Though Default overrides the LVDS class in this case.
Though clearance shouldnât have any affect as that should be external to the differential pair.
There are a few things at play here (and I havenât understood whatâs going on enough yet to figure out if there are bugs, expected behaviour, missing implementation, etc). Iâve also flagged this thread to our router expert, who hopefully will take a look.
In terms of netclass values - all that matters is the effective netclass constructed from the priority-ordered values from the constituent netclasses. In this case, the LVDS class is higher priority than Default, so any values there should take precedence. If a value that is set in Default is overriding one which is also set in LVDS, then we potentially have a bug.
Then we add on routing specifics - I think that the diff pair gap will only be applied when routing with the diff pair routing mode (and it should be checked by DRC too). So moving single tracks could violate this.
Then you add on top quite when clearance etc. from DRC rules overrides defaults and Netclass values, and thereâs a potentially bit of a complex beast here. I need to have a play to understand it fully.
Ok, thanks, I added an edit to my post above regarding the clearance setting and tried a couple of settings.
Thereâs likely something in the interplay of netclass values and DRC rule values here, will need a bit of investigation to get to the bottom of.
Thatâs great thanks.
It has similar behaviour in 8.0.9, except the LVDS class takes precedence over the Default class.
In both changing either the clearance or the DP Gap in the class to less than or equal to the custom rule diff_pair_gap value will allow it.
Iâm not certain, but shouldnât the custom rule take precedence, and the clearance be separate from the DP Gap? As you may want a DP Gap of 0.15mm but a clearance larger than that between a DP and another track?
Reading from the PCB Editor manual:
The track widths and via sizes defined for each net class are used when the track width and via size controls are set to âuse netclass valuesâ in the PCB editor. These widths and sizes are considered the default, or optimal, sizes for that net class. They are not minimum or maximum values. Manually changing the track width or via size to a different value from that defined in the Net Classes section will not result in a DRC violation. To restrict track width or via size to specific values, use Custom Rules.
It does appear that the values in the net classes are supposed to be optimal values not minimum ones.
Anyway, Iâll wait and see what the investigation returns.
