Hi Geeks,
i recently ran into an issue in kicad 8.0 Simulation.
the issue is as below
i am designing a simple Mosfet based switch using N-MOS as shown in the attached picture.
it was part of a bigger circuit, But for testing purpose all the other circuits were removed and only this NMOS switch was simulated.
As you can see in the Simulation graph, when EN is HIGH , Mosfet is turning OFF and vice versa.
But in reality NMOS should work the opposite way right.
I found it strange,
the MOSFET model was taken from this link
Please help me understand where’s the issue was
Thank you
From the linked model I see that it is not just an NMOS but it also has a PMOS inside, a resistor, and some other stuff.
The main reason may be missing or wrong pin assignment.
As ngspice requires the sequence 1 drain 2 gate 3 source, and the symbol has a different numeration, you have to take care of this. Unfortunately the Eeschema image alone does not tell anything about it.
For an example of the pin assigment you might read my tutorial at KiCad Eeschema as GUI for ngspice, tutorial for setting up the simulation .
1 Like
This zip file has the following modifications that may help resolve the issue.
AO3400A.zip (1.0 MB)
UPDATED COMPACT AO3400.CIR SPICE MODEL (ALSO IN ZIP FILE)
* AO3400 30V N-CHANNEL NMOSFET
*
* CONNECTIONS: G S D
* | | |
.SUBCKT AO3400 1 2 4
M1 3 1 2 2 NMOS W=998956u L=1.0u
M2 2 1 2 4 PMOS W=998956u L=0.4u
R1 4 3 RTEMP 15E-3
CGS 1 2 225E-12
DBD 2 3 DBD
*
.MODEL NMOS NMOS (LEVEL=3 TOX=2.5E-8 RS=2E-4 RD=0 NSUB=1.6E17
+ kp=3E-5 UO=600 THETA=0 VMAX=0 XJ=4E-7 KAPPA=1.1
+ ETA=0 TPG=1 IS=0 LD=0 CGSO=0 CGDO=0 CGBO=0 NFS=2E10 DELTA=0.1)
*
.MODEL PMOS PMOS (LEVEL=3 TOX=2.5E-8 NSUB=2.0E16 TPG=-1)
*
.MODEL DBD D (CJO=690E-12 VJ=0.6 M=0.3
+ RS=0.005 FC=0.5 IS=1E-11 TT=1.5E-8 N=1.0 BV=36 IBV=1E-4)
*
.MODEL RTEMP RES (TC1=6.5E-3 TC2=1E-6)
*
.ENDS
1 Like
@holger @invntefx I agree to your point that ngspice requires naming as below
1 drain 2 gate 3 source
But that contradicts with existing footprints, because usual SOT-23 footprints would be numbered as
1 Gate 2 Source 3 Drain as shown below in the picture.
So is there any work around to make it work with ngspice and existing footprints at the same time.
SOT-23 Mosfet pinout link
You have to be careful.
There are basically two model types used in KiCad/Eeschema (or any other spice).
There are intrinsic models, e.g. for bipolar, MOS, JFET and some others. Their characteristics is described by the model parameters assembled in a .model line like
.model BC549C NPN(Is=7.049f Xti=3 Eg=1.11 Vaf=23.89 Bf=493.2 Ise=99.2f Ne=1.829 Ikf=.1542 Nk=.6339 Xtb=1.5 Br=2.886 Isc=7.371p Nc=1.508 Ikr=5.426 Rc=1.175 Cjc=5.5p Mjc=.3132 Vjc=.4924 Fc=.5 Cje=11.5p Mje=.6558 Vje=.5 Tr=10n Tf=420.3p Itf=1.374 Xtf=39.42 Vtf=10 Vceo=30 Icrating=100m mfg=Philips).
Here the node sequence of the model is prescribed by ngspice, e.g. C, B, E, or D, G, S. If the symbol has a different pin numbering, you have to use the pin assignment feature in Eeschema.
Then there are the subcircuit models. They are characterized by a starting .subckt line and a corresponding .ends line. In between a complete model is described, typically made by other ngspice elements. An example is the model of the AO3400 power transistor, cited above, which is starting with the line
.SUBCKT AO3400 1 2 4
Here the node sequence of the model is given by the sequence (position of the nodes) in the .subckt line. The model description says that the sequence is G S D. The symbol has 1 (G), 2 (S) 3 (D), so the same sequence as the model already has. Thus there is no further pin assignment necessary. If there was a deviation, then again a suitable pin assignment is needed.
Btw. the numbers on the .subckt line (here 1 2 4) are node names used internally within the subcircuit. Other models might even have texts like in+ in- out as node names. For the pin assignment only the position of the node in the .subckt line is of interest.
yes @invntefx , thank you for the files.
they solved the issues, to conclude pin assignment should be taken care off
As @holger stated the included SPICE will automatically assign correct pinout
for both symbol and footprint as well as ngspice simulation.
NOTE: Intrinsic models (.MODEL) use the filename extension “.MOD” by default.
Subcircuit (.SUBCKT) models use the filename extension “.CIR” by default.
SPICE Libraries contain both the above and use the “.LIB” filename extension by default.
UPDATED COMPACT AO3400.CIR SPICE MODEL (ALSO IN ZIP FILE)
* AO3400 30V N-CHANNEL NMOSFET
*
* CONNECTIONS: G S D
* | | |
.SUBCKT AO3400 1 2 4
M1 3 1 2 2 NMOS W=998956u L=1.0u
M2 2 1 2 4 PMOS W=998956u L=0.4u
R1 4 3 RTEMP 15E-3
CGS 1 2 225E-12
DBD 2 3 DBD
*
.MODEL NMOS NMOS (LEVEL=3 TOX=2.5E-8 RS=2E-4 RD=0 NSUB=1.6E17
+ kp=3E-5 UO=600 THETA=0 VMAX=0 XJ=4E-7 KAPPA=1.1
+ ETA=0 TPG=1 IS=0 LD=0 CGSO=0 CGDO=0 CGBO=0 NFS=2E10 DELTA=0.1)
*
.MODEL PMOS PMOS (LEVEL=3 TOX=2.5E-8 NSUB=2.0E16 TPG=-1)
*
.MODEL DBD D (CJO=690E-12 VJ=0.6 M=0.3
+ RS=0.005 FC=0.5 IS=1E-11 TT=1.5E-8 N=1.0 BV=36 IBV=1E-4)
*
.MODEL RTEMP RES (TC1=6.5E-3 TC2=1E-6)
*
.ENDS