I have a KiCAD 5.1 project that simulates fine. I’ve downloaded KiCAD 6.0.7, opened the project and when I try to simulate it I get a load of model errors.
Looking at one of the problem lines in the generated spice netlist I see:
so KiCAD 6 has stripped the model off of some of my parts. The schematic is large so this is not so easily fixed manually. The question is, what is happening? I have AUY21 defined in a text block on the schematic:
You have chosen an ‘uncommon’ way to add the .model via text on the schematic. This may have worked on KiCad 5, may or may not work on translating KiCad 5 to Kicad 6 or directly on KiCad 6.
Without any test project published here it is impossible to analyze anything.
You may need to attach the model in the usual way (via loading from a file) to each instance in KiCad 6.
That is… unfortunate because there are maybe 100 transistors and diodes that all need models and giving them all a .lib is not as user-friendly as just putting the models into a text block like I can do with v5. Seems like a step backwards.
If I export the spice netlist from v6 I see the entire text block contents are included and the diodes and other transistors all have their models assigned which are defined in the text block, so it seems to be partially working. Just that one transistor definition is not being applied based on the name.
This ‘fixes’ it:
Move pointer over transistor and press ‘e’
Click on Spice Model
Change the model from AUY21 to AUY2
Change the model from AUY2 to AUY21
Click on OK
now the Spice_Model field is added and the netlist output is correct. So it seems this is a bug in conversion from V5 to V6, either not picking the model up automatically from the name or removing the model, but only for the one transistor model, not any of the others.
Uhhh… after fixing the missing model problems the simulation gives a completely wrong waveform on the output. Works fine with KiCAD 5. I tried the pspice compatibility mode - same.
Running external ngspice-36 from KiCAD 6 produces the same mangled waveform, so it’s not a spice issue, it is something to do wtih generating the netlist.
What changes were made to the simulation between KiCAD 5.1.12 (Windows) and KiCAD 6.0.7 (Windows)?
Here are the netlists from V5 and V6. Looks like most of the lines are now output in a different order making any changes very difficult to spot.
Seems to be something to do with ground. Probing my ground net gives 13V. I have the pspice ground symbol connected to a global “0” label which is connected to a regular ground symbol. pspice compatibility mode is on.
I’ve never had this issue myself, but the whole spice model thing is tedious in itself.
The most efficient way I’ve found is to make one perfect transistor or diode with spice model and all the works, and then use the “duplicate” function for placement. You’ll still need to assign all the part designators (Q1, Q2…) by hand again, though.
Something is still not right. Every voltage is 4V too low. If I probe the output of a DC voltage source set to 22V it shows as 18V. So it must still be a ground issue somewhere.
Best is to analyze the netlist sent to ngspice.
Eeschema–> File–> Export → Netlist → Export Netlist
You will see the naming conventions of the nodes on top sheet and sub sheets.
Maybe adding a .global gnd
in the text box on the main sheet will help.
I have no idea because as I wrote KiCAD5 and KICAD6 output the lines in different orders so it is impossible to use Winmerge or something like that to compare. I attached them to a previous post - they are large. Did you see?
There appears to be a fundamental difference between how KiCAD5 and KiCAD6 expect the schematic when simulation is being used, but it is a struggle of trial and error to work it out.
