JLCPCB hasl bridges on the default transistor footprint

Hey there,

It looks like I got some occasional HASL bridging on the default transistor footprint from JLCPCB. This shorts two pins. Not every transistor footprint has the bridge, but it seems odd.

Has anyone else had this issue with JLCPCB?

Looking closer, it looks like there’s no solder mask between the pads. Is that the expected behavior?

Thanks for your help.

I use them a lot for SMD with very fine pitch and typically don’t run into this kind of issue.
The spacing between the pads on the TO-92 footprint is 10 mils so should be well within their tolerances. Maybe look at the Pcbnew board setup and ensure the Solder mask clearance and minimum width are set correctly.

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Okay I think I see what happened.

In the board setup, the mask clearance is .051mm. The minimum width was 0.25mm. The actual width of the mask between the pads would have been .127mm. That would explain why there was no solder mask there.

So the next question is, for JLCPCB/oshpark/pcbway/etc are there default board setups? I noticed that JLCPCB capabilities doesn’t seem to mention the minimum spacing of solder mask to pad or minimum width of solder mask. Or maybe I just overlooked it or don’t know where to look…

There is a lot of solder on those pads, maybe the HASL process is not set up right.
The holes in the transistor footprint look a bit large for the pad size too

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So this affected about 1 in 10 transistor footprints. I’m not a HASL expert, but it seems like the solder mask not going through entirely had an effect.

It does look like they increased the size of the hole. The hole in kicad was .75mm. It looks like they used a .9mm drill.



Good HASL edge on

Bad HASL edge on

Nice Photos!
Blah Blah Blah added text to get 20 character minimum.

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Thanks. Pictures were taken with the Andonstar microscope.

It’s hard to see but the good HASL is less than half the height of the bad HASL edge on.

And after looking at the quality of the mask, I think the tolerances on the solder masks can go a lot lower in the board setup.

Also it’s worth noting that the 4 layer boards have better tolerances than the 2 layer boards from JLCPCB, so I’m guessing they may limit the number of drills for their 2 layer process.

The JLCPCB capabilities say the 4 layer boards have much tighter tolerances. Sooo…

Around 1995 or so, I powered up a 2-layer board that I had designed, and it did not work…open connection somewhere. It turned out that one via was open (not connected.) I guess the plating was cracked or something. Back then, I doubt that we were buying boards from foreign suppliers. I think that even American fabs can produce bad boards, at least at that time. Rightly or wrongly, this memory has led me to (almost always) double up on vias. Redundant vias everywhere. Am I nuts? :frowning:

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No more nuts than a place I used to work. They also had cracked vias before I started working there, so their solution was to not tent vias and fill them all with solder. Our board runs were all on the order of 10 or less, so we built the boards up in-house by hand. So, I was one of the lucky ones to fill vias on hand-assembled THT boards. If you thought hand soldering a couple dozen DIP packages was tedious, don’t forget to also fill in the vias… :disappointed:

I’m not sure this is even a problem.
THT is supposed to be wave soldered, and during the soldering liters of molten solder are poured all over the board. Have any of these bridges persisted after soldering?

With no pins in the holes the solder is much more likely to bridge the narrow gap between the pads than during the soldering process, where the surface tension is more likely to pull the solder to the pins and pad holes.

But be honest. TO-92 is an absolutely ancient package from an era when automated PCB assembly did not even exist. The legs of this part were probably never intended to put straight into a PCB but meant to be bent apart during assembly, and there are machines to do this, just as for cutting and bending the wires of THT resistors.

I’ve also wondered about the very narrow spacing of the pads in KiCad’s library symbol, but it’s not as if you’ve got not alternative. I count some 30+ variants int the KiCad default lib’s:

Reminds me of a hobby project I built on 1 hole per pad vero board. there was a hair on the PCB during production which shorted some 6 pads together with a very narrow copper track which was under the solder mask and almost impossible to see, especially after I soldered some switches over it.

Did you ordered the pcbs including flying probe testing (it should be default @jlc)? That test should have discovered the issue.

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JLCPCB claim a hole tolerance of ±0.08mm, that is less than you seem to have.
The theoretical maximum for a TO-92 lead is 0.717mm diagonal, but I have never met one maximum both X and Y
I used to have oversized holes for old Panasonic through hole stuffing machines and got frequent dry joints.

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Yes, the board was fully tested. It may have been tested before HASL though.

I tried a hot air rework station, but it didn’t seem to flow back.

Also there are other components in kicad with tight footprints like this, notably a 4 pin RGB led has tight spacing similar to this.

I’ll have more time to play around this evening. So I’ll see if I can get it to flow with flux, etc.

Hot air rework station needs a lot of time to heat up the board, and also lacks mechanical stimulus.

Also, no solder work can be done comfortably without flux. So if you want to rework manually I would use some flux and a soldering station with a big flat tip.

Flying probe test should leave pin prick sized evidence on most pads, but if these pin pricks are under the HASL then evidence may be hard to get.

@davidsrsb The top side of the board looks fine, but the bottom side of the board has excess solder. There’s a M2.5 PTH that looks flat on the top side, but rather bumpy on the bottom side.

Huh. Something to note if I were going to do a production run of these using JLCPCB I guess.

Thanks for the help. :slight_smile:

For fabrication data, it is best to set the clearance at 0, and not set the minimum width. Ideally, this is what one wants. Of course, this cannot be made because of fabrication tolerances. It is up to the fabricator to tweak the data on him CAM software to fit his production process. Trying to do the fabricators job for hum only makes his life more difficult. In this case, setting up a minimum width removed the bridge, probably needlessly making it harder for the fabricator.

Is there some reason those are not set to zero by default? It seems like for most use cases those defaults are unnecessary, and maybe makes for a bad user experience, too.

Also, it seems hard to see what the mask looks like while editing in pcbnew. Is there a way to see how it will render without plotting? Or do you have to plot gerbers to see what the solder mask will look like for a given footprint?

I do not know why the default is not zero. It is a good suggestion, it would avoid problems. A neutral default is best unless there is a very clear reason why it needs something else. Any other default will nearly always be wrong, and thus useless.

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This may well be a copper problem underneath the HASL. Probably so, actually, since you don’t succeed in reflowing it back in place.