The analysis always generates the same error.
The message :
“Edge.Cuts.gbr(Board Outline Layer) :Gerber file with a board outline”
jlcpcb GerberViewer (empty outline layer)
On Kicad Gerber viewer, the plot appears correctly.
I changed all the export settings. Each time, the same error occurs.
Can you help me ?
Your plot form should somewhat look like this.
Especially the right hand side section!
This set up works well with jlc.
Thank you Jos,
The problem remains. I sent the files to Seeed which seems to accept them.
Not enough to go on really.
I checked with a gerber set of mine and the website works. No errors.
My files are named like this (by KiCAD, straight out):
We’d at least need a screenshot of your settings for plot of the drill holes and the gerbers, like this:
As Joan shows above, I always Check the box for “Exclude PCB edge layer from other layers”. Although I do not use Protel naming.
Did you get an Edge Cuts file? Just look at that single file in Gerb Viewer.
The point by @iabarry is that some (perhaps most?) board fabricators DO NOT want the board outline shown in any Gerber file except the actual Edge.Cuts file. (Don’t ask me how they ensure layer-to-layer registration, since I haven’t seen a “target” or “bullseye” on a PCB layout for a decade or more.) The error message may not be squawking about the Edge.Cuts layer, but rather complaining that Edge.Cuts information was found on other layers.
The CAM tools aggregate all the different layouts and place it into a super layout which will have those marks for their processes, no?
The only thing not covered by that is for pick&place machines, once they assemble the boards, which is why one needs some markers for that.
But that’s just me guessing really
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.