Issues with zone fills violating DRC

I’m having a couple issues with zone fills misbehaving. Not sure if this is something related to my settings or potentially a bug.

I’m using KiCad 7.0.7 on MacOS (build 22A8380).

In a few places in my design where features are close together and a zone fill attempts to go around them, it’s rounding off the corners of each side in such a way that they intersect, leading to a “Copper connection too narrow” DRC error. See examples below.

My board level “Arc/circle approximated by segments max allowed deviation” is set to 0.001 mm (appears to be the minimum allowed), which eliminated some instances of this issue vs the default 0.005 mm setting, but didn’t clear it up entirely. Minimum connection width is set to 0.15 mm. The zones in question are set to 0.25 mm clearance, 0.25 mm minimum width.

Another related issue that may have the same root cause, in some places the zone fills are creating gaps that are definitely smaller than the minimum clearance setting for the board, however they are not being flagged by DRC, such as the one below:

How have other folks handled this situation? Seems like it would be a fairly common issue for higher-density designs.

Thanks!

Can you upload a example project with this problem? (You may have to browse the forum a bit before you have permission to do that)

I have seen these too and it’s related to the settings. If the via radii plus via clearances plus minimum copper width for the zone is just a tiny bit too small to fit in the distance between the via’s.

To show the effect clearly, I have made a test project in which the distance between via’s is incremented in very tiny amounts. A grid setting of 0.01mm was still too coarse to show the effect, so I made use of the knowledge of an ancient Greek to make smaller distance increments.

The effect is much easier to observe when you zoom in on the via’s in KiCad itself, so here is the project:
2023-09-22_asdf_vias.zip (21.5 KB)

I do not get the Copper connection too narrow DRC violation on this project though. For which via’s do you get that? I assume you only get that when such a bridge is the only connection, and in that case KiCad is just right. The interactive router in KiCad can shove things around quite a lot, and this can disrupt connectivity in zones. Sometimes I draw a (wide) track between some pads in different parts of a zone, to make sure parts of a zone can not become isolated when stuff gets shoved around.

I do not see this as “misbehaving”, but just a result of distances between items. I do agree that it is not optimal. Thinking about houw this could be improved in KiCad. It may be possible to add a “forbidden range” in distance between items, so the items are either so close that the zone can not connect at all (right side of my example) or the parts are so far apart that the zone connects fully (Left side), but the distance in between is prohibited. That would be difficult to implement though, because this can also occur when the properties of any of the involved objects change.

I do not get the “Copper connection too narrow” DRC violation on this project though

In your example project the Board setup–>design rules–>Constraints value–>Minimum connection width is set to zero.

If you set this value to 0,1mm you get the warning on one of the middle vias.

Indeed.
I set it to 0.2mm, and now I get 6 DRC violations for this:

2023-09-22T16:32_asdf_vias.zip (21.5 KB)

But overall, the way I see it, it is just a result of the via placement, and not something that could or should be fixed in KiCad itself.

Thanks for the replies. I can’t share the project itself since it’s a work thing but paulvdh’s recreation hits the problem exactly.

For now I’ll just adjust design rules and zone fill parameters to avoid this, or just waive the DRCs. In practice, the gaps / necks are so small they may not even show up in the physical product, or the vendor may clean them up automatically per their process rules. I’ve had this show up on personal projects as well and waived the DRCs without causing DFM complaints but it probably depends how picky the vendor is.

Personally I do think it’s valid to consider this a bug, nothing that’s auto-generated should be creating DRC errors, and with other tools I’ve used the copper fill would be pulled back automatically in this case. But frankly I’ve also had way more dangerous problems with zone fills in other tools as well that could have caused big issues - this is at worst a little annoying. If I get inspired maybe I’ll take a look at the zone fill code and submit a patch at some point but I’ll probably just work around it for the time being.

Thanks again for the discussion, I appreciate the help!

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I think that there were some fill changes in what is now 7.0.8 rc1

I am having the same issue and I would definitely classify it as a bug with the zone filler.

If a zone is set to have a minimum width of 10 mil, it should be impossible to have these thin connections between vias (or other features) that are ~4 mils thick. I definitely shouldn’t be getting errors about violating my 6 mil min width constraint.

Together with moving to KiCad (4.0.7 those time) I changed my designs from mils to mm. Because of this one of first checks I have done with KiCad was to go with 0.2mm track between two pads with 0.6mm distance between them with the clearance being set to 0.2mm. And it was not possible. So I have changed clearance to 0.199mm and I use it till now.
Didn’t checked myself the problem you discuss, but looking at pictures I suppose it can be the same kind of problem. If yes I would not call it a (logical) zone filler bug but simply number rounding problem.
Try to modify by (not noticeable) 0.001mm zone Clearance or Minimum width setting to check if it is that problem.

I have this also. I can change the settings but this just moves problems from one area of the board to another. However this is a bug as said above as should not be possible for this to happen whatever the settings.
Also probably related, I have copper islands that are not being removed, even with the check box ticked to always, or setting a very small area.
This is change in behavior from previous versions.
To complete my upcoming projects I’m going to have to employ some time consuming workarounds until this is fixed.

You didn’t say what version of 7.0 you are using ?

Application: KiCad PCB Editor x64 on x64

Version: 7.0.9, release build

Libraries:
wxWidgets 3.2.3
FreeType 2.12.1
HarfBuzz 8.2.1
FontConfig 2.14.2
libcurl/8.4.0-DEV Schannel zlib/1.3

Platform: Windows 10 (build 19045), 64-bit edition, 64 bit, Little endian, wxMSW

Build Info:
Date: Nov 5 2023 19:26:40
wxWidgets: 3.2.3 (wchar_t,wx containers)
Boost: 1.83.0
OCC: 7.7.1
Curl: 8.4.0-DEV
ngspice: 41
Compiler: Visual C++ 1936 without C++ ABI

Build settings:
KICAD_SPICE=ON


I reduced the arc/circle setting to 0.001, but even though (as shown in the screenshot) there is room to fill it doesn’t merge the two ends correctly.