Hi,
How can avoid the creation of the small island?
Thank you for the help
Maybe with “zone properties dialog–>remove islands” setting.
But the small copper area seems still connected to the main copper area. So I’m not sure if that’s already count as real island.
No,
It didn’t work.
The problem is that the DRC gave me an error for the minimum connection width due to the island which i didn’t want to be created.
Can you paste your version info here please, you can get it from KiCad > Help > About KiCad > Copy Version Info
Posting the version info won’t help here. This is an artifact of the zone boundary algorithm. KiCad calculates an outline for the zone, and then fills it, but this outline is drawn with a certain line width. If a neck is narrower then the line width for the zone outline, KiCad creates these artifacts.This has been mentioned by others a few times too. I think there is already an issue for it on gitlab.
I think there are few solutions to select one:
- specify a little smaller “Minimum width” in Zone properties that should allow KiCad to make this connection more solid,
- move +48V via little up it can have the same effect,
- reduce via diameter minimally,
- make clearance between zone and +48V little smaller,
- make clearance between copper and Edge.Cuts little smaller,
- edit zone border to exclude this island from zone,
- add small rule area to exclude this island from being filled.
I believe at least one of these methods should be possible for you to use.
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I think change the electrical constraints (clearence, via size) can’t be a solution because if i change this settings they change in all the pcb not only in this part
I thought I had remembered a discussion about this in the last few months and a suggestion that it would be improved . . . might have been my imagination, I hope not 
Yesterday I could not recall the details, but Piotr is right. by editing the properties of a zone and setting the Minimum width to a smaller value, KiCad uses a thinner line for the outline of the zone, and this makes the connection to this island “more solid”.
You will be glad to hear I’m not losing it just yet (well not all of it) . . . this is what I was thinking of . . .
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This is on by default in the 9.0 release
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Although much less than in 8.0, I still encounter the “kissing” issue in 9.0, e.g.,
As @MarcoPianca noticed, the “global” zone or other properties change is not always a viable solution as it affects the whole board. Nevertheless (contrary to 8.0), these are few enough to cope with them by manual adjustment of the board in problematic places (at least in my design).
It seems to me that in some cases a decrease of Maximum allowed deviation in Arc/circle approximated by segments (in Design rules → Constraints) may help.
I bet that you can always constructed cases where you get those (let me call it) artifacts. And sometimes, you find them by incidence.
I personally would have moved the via a tad.
Thank you for the tip. I am able to deal with it. I just want to report the issue in v9.0 is vastly reduced but not completely eliminated. May be you are right and some cases are hard to cover (the one above is real-life, not artificial).
You misunderstood me. I am sure you can do it and you know how to do it.
My point was, that this is and error of quantization. A rounding error coming from floats representation (I assume). And no matter how hard you try to fix the software, it will happen again.
Now I understand, thank you for the explanation.
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