I am trying to create a copper area based on the chip manufactures recommendations, but kicad is giving me cutouts on pin 8 regardless of what i choose in clearance overrides.
I believe i am missing the correct setting here.
ok solved i think by setting the clearance for the lower pad right down, assuming this was the best way to achieve it.
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I’d have made these changes in the footprint editor using the Graphic Polygon tool, so I didn’t have to alter clearance settings.
While your solution may work for you I don’t think this is a good solution and I would not recommend it to others. Reducing the pad clearance that much potentially opens clearance issues with other tracks (depending on how pad 6 is normally connected) which may or may not be detected later by the DRC.
Looking at the place between pad 9 and the zone: the zone is still not exactly filled until the drawed border, despite it’s outside from the clearance outline of pad9.
You could play with the following zone settings (in the Copper Zone properties dialog):
- clearance
- minimum width
- pad connections: solid
Also all other clearance settings (from Board-setup–>designrules–>Constraints and Board-setup–>designrules–>Net classes are important) are affecting the zone filling algorithm.
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I also think it is not such a good solution.
The heavy copper area may change the heating rate in that corner of the IC, and influence the time needed for soldering. I would make the zone smaller, so it does not touch the pads at all, and then draw short tracks into the zone for the actual connections.
Also, during rework or repair, solder bridges between pins are a distraction, even if they are by design and no fault on their own.
I am only going down this route as the chip manufacture recommends this
I previously had this manufactured using this layout, and can agree the joined pins made flowing the chip into place with hot air a bit harder than normal.
But i have more noise than i would like on the output so wanted to revert to actual manufacturer reccomendations, especially separating the power ground and other grounds
It is a pity the layout example was not posted at the beginning of the topic.
It would have been so much easier to make comments on how to achieve the result required.
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Apologies, youre right that would have made sense/
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The comment wasn’t really aimed at you in particular. This happens a lot on this forum. Guesswork because there is only half a story and mind reading is difficult over the internet. 
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Well, uhm, it looks nice.
But what is it?
Your earlier “Layout example” shows an L1, which suggests an inductor, while your latest and greatest screenshot shows a big fat D1 (Diode?). I’m guessing (see jmk’s previous post) it’s an smps circuit, but don’t know which, my crystal ball is out for repair. I’m also seeing some ratsnest lines north of R2. Are those the voltage divider for sensing the voltage?
I also do not understand the GND track in between the diode (inductor?) tracks. If it’s an SMPS, my guess would be this will generate noise. As far as I know it’s best to keep both wires to the inductor as close together as possible to reduce the loop area.
HI Paul, apologies. D1 is an inductor i changed the component and the new symbol/footprint had a D designator prefix for some reason, changed to L1 to avoid confusion.
Yes you are right, above R2 is the voltage divider to select the output voltage via the feeback pin.
Here is the context
Boost converter using TPS63070 chip
Webench designed circuit
Manufacturers suggested layout
My Interpretation of the layout (avoiding vias in pads)
I “had” an uninterrupted ground plane until i added this inductor as they show. In their example i can only assume they have a power and ground area on the top of the board tied back to dedicated power and ground planes on other layers at least that whats it seems to imply.
I only have signals and power on the top layer and just ground on the bottom, as such ive kept the “powerground” seperate as they have suggested on the top and then pinned it to the bottom layer ground plane by the 10 vias.
So the difference between old design and this one for my circuit is really is have i achieved these notes from the datasheet, and will it ultimately reduce noise.
Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise.
A ceramic capacitor each, as close as possible from the VIN pin to GND and one from the VOUT pin to GND, shown as C1 and C4 in the layout proposal are used to suppress high frequency noise.
use wide and short traces for the main current path and for the power ground
connection.
Edit:
Just noticed my footprint for the chip is incorrect
I do not understand the layout example from that manufacturer. As far as I know an important goal is to minimize loop area around the wires to the inductor. I would put the tracks on the top side without via’s and also put them as close to each other as possible for as long as possible, Right up to the center of L1, and then split the tracks horizontally in a T. Maybe it’s also better to remove a piece of the GND plane around the inductor, to prevent a stray field from inducing any current into the GND plane, but I am not sure if that matters.
I would add an extra GND via just north of pin 10 to the GND plane before the inductor tracks hug each other.
Put the resistors for the voltage feedback closer together so they pick up less noise. Use the courtyard as a reference of how close you can put them together.
What sort of an idiot puts stuff like this in a datasheet:
IC descriptions have been standardized on top view for 40+ years and adding the bottom view also just adds more room for confusion.
But I’m no expert in SMPS layouts
Also, do not just rely on a recommendation from a single datasheet. It’s nice to have a datasheet for reference, but I do not trust recommendations like this very much. Do some research into the direction of “hot loop” for SMPS design.
And last, if you really want to optimize for reduced noise, then consider making a few different layouts, put them all on a single PCB next to each other and test it yourself. PCB’s are cheap these days, so the main cost will be time. You can also add an LC filter at the end to filter out more noise.
I don’t know how this exact IC works (as both L ends are hidden inside it) and will not search for it, but…
In any DCDC circuit the L ends rapidly jamps against each other. Increasing capacitance between them may be not the best idea. What is needed to be minimized are difference between current loops in both DCDC working stages. I don’t know where they are here but probably C1 and C4 are in them.
This is nonsense. The inductor itself is already a coil of closely packed wire with lots of capacitance. adding a few pF on 10mm of track is negligible. As far as I know, the thing to optimize here is the open area between the tracks, because this creates a magnetic stray field. It acts as a loop antenna.
Yes, true, this is what this “hot loop” I mentioned earlier is all about. It explains in detail how the current paths change during switching of the SMPS, their influence and what to optimize for.
I won’t persist. Probably you are right.
Do you remember the following discussion:
and information written by BobZ who spend his live designing DCDC?
I learned then that part of loop containing L is not critical to be minimized and worried about. It is because current in L changes slowly (triangle shape without jumps). Critical are parts of current loops where current has jumps.
Thanks @paulvdh,
This makes me happier that i have nothing but ground on the bottom layer. I think i understood you correctly and now have this. Like you said i might run this board and test it against the one i already have and see if ive actaully made any difference… Probably add some pads for an LC filter and stop being afraid of the fear of creating instability by accident.
I always like to have only GND at bottom 
Two associations:
- at their pcb (and at your first) connections to L look like having high current (many vias in their picture),
- if good/short connection between right and left part of GND at top is critical (I don’t know but their suggestion for C1,C4…) what about connecting them with 0R. It will be much shorter way than through vias (or two 0Rs paralel).