For reference, this is the output on the previous layout/design before this one.
I have just realised the the 40mv ripple is probably expected as i am running at little to no load, so the datasheet implies that at 50mv ripple is to be expected here…
Dont know what the spikes are at 720mv and embarked on this redesign on the basis that the manufacture knows best and should probably start from their recommendations before i think about the reasons behind anything further.
at their pcb (and at your first) connections to L look like having high current (many vias in their picture),
I’ve hit the limit of trace width i can bring out of the pins i think, i can try and squeeze a bit more maybe… currently at 0.25mm
what about connecting them with 0R. It will be much shorter way than through vias (or two 0Rs paralel)
.I like this idea as the whole reason for the redesign was the implied need for some separation of pwrgnd and gnd.
I change track width on the go many times.
For example I prefer 0.25 and from 0.4 raster IC I have to go out with 0.2, but shortly I change them to 0.25 for their farther way. If I go with 1mm Vcc track to small pad I change it to narrower just before that pad to not have the track end (snapped to pad center) stick out from the other pad side.
You will not be able to place L and 0R in the same space 
Lol i had already realized and am fixing now…
I’m not sure if this via between tracks to L is really needed as there are 3 on the other pad side.
I thought about it a bit more…
In an SMPS, the current switches from the input capacitors into the inductor, and then from the inductor to the output capacitors. As a result, there is also a lot of GND current switching between the input and the output capacitors. Also, as this is a combined buck / boost design, in boost mode there is even more GND current, as one side of the inductor is shorted to GND to “charge” it’s magnetic field.
Therefore I think it is better to put the via’s back into the tracks to the inductor and put the big bridge on the top of the PCB back. Then also remove half of the via’s in this ground bridge, and cluster the rest together. (For example 4 in a square) This will create a sort of star ground, where the via’s only carry DC current, while all the switching GND current stays on the top layer of the PCB.
Does this make sense?
It’s now also drifting quite far off topic. Some people try to limit the scope of this forum to how KiCad works only. And there are probably also better forums for SMPS layout design tips.
I think that was suggestions from @paulvdh ealrier in the thread, and actaully that is the power ground that was originally connected to the larger plane we just connected via the zero ohm resistor and i think the original reason they had the inductor tracks on the reverse side so that this plane was all connected…
I think this via is to mitigate the loss of the connection to the power gnd plane.
Fixed inductor placement … doh.
Thats fair i got my answer to how to use the copper fills and clearances.
Appreciate all the extra help/tips etc thanks @paulvdh @Piotr much appreciated.
You lost L connections 
Two more suggestions.
The intention is to create a local “star ground”. There is no need to connect the GND on the bottom layer together in that particular spot. In this particular situation, the effect you want is the opposite of normal PCB design. Normally you want a good GND plane under all signal wires (especially digital stuff with steep flanks), but in this particular case you want to keep as much of the AC current in the horizontal track as you can. Possibly it’s even (marginally) better to move all four via’s to the rightmost corner near the connector.
Possible third suggestion. It may be better to not put a GND plane under the inductor itself. The stray field inducess eddy current losses and noise in the GND plane under it. But this is a guess and would need some research. It also depends on the design of the inductor.
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