I’ve searched all over the forum and can’t find a solution for this “auto-connect” anomaly of tracks when they overlap.
Not very well . . .
There was a thread just last week about this exact thing.
To be honest, I’ve found it better to use an outside search engine than the Discourse internal search function.
And if you have read those threads, I believe you already know that issues can be voted for in the issue database. Specifically, what doesn’t help is aggressive complaining here. I say this because your topic subject shows you are frustrated, not because you would have said something aggressive – yet. If the discussion heats up we will close it quickly.
Yep, people have been screaming about this for years… and rightfully so. I mean, what’s the point of having an advanced ERC tool when you can create critical errors literally with one bad mouse move, and with absolutely no warning?
To be fair, schematic editors in Orcad and Altium have this shitty behavior too, but at least they bother to warn the user (red signs start to pop up near cursor). This feature has been requested in KiCad about a year ago, so you could help moving it forward by upvoting it on Gitlab. Now, it’s no secret that past and present KiCad developers view the schematic editor only as necessary evil, although there are objective reasons behind that, too. But they do react to community feedback, so go there and upvote it.
Hysterically ?
I’d prefer to see an option to lock all or parts of a schematic to prevent inadvertent changes . . .
Yeah, and I’d like KiCad to have Eagle-like persistent net names. I.e. that net name is intrinsic property (field) of wires themselves, and not defined by flimsy separate labels which you can accidentally move away with no warning. In Eagle, labels are only indicators and they’re permanently tied with given net, even when you move them away. When you change a net name, they automatically change, too. In other words, no KiCad-like net name conflicts are possible. And Eagle actually asks you before merging two nets into one, either accidentally or intentionally. That way, you wouldn’t need clunky workarounds like locking parts of a schematic.
Of course, I know that’s not happening, ever. KiCad is not Eagle, like it’s not Orcad or Altium or DipTrace.
DesignSpark does it too
Really: Coming from other tools, (I have seen lots of different ones) I love the behaviour of KiCad in this respect. I use this quite often as a feature to change connections (i.e. placing labels or components across existing connections or pins). Sure, Kicad could always ask back If I really want to do what I do but I think when working carefully this is not really a big deal.
That said. The proposed feature of highlighting connection changes (e.g . by red dots) would be cool - got me upvoting that feature request =)
I don’t even know what this means, even if I look past somebody telling me what my views on central components of Kicad apparently are.
I thought this thread provided a good opportunity for me to exercise my new Visio…uh…video skills based upon some advice from another recent thread.
What I see here is that if a pin or wire connection or wire corner lands on a wire, I get a new connection. If wires just cross, I do not. Does everyone agree with that?
BTW I made this video with Microsoft snipping tool. That original file is 17 MB. With handbrake I compressed it down to 318 KB.
Application: KiCad Schematic Editor x64 on x64
Version: 8.0.8-182-g34ce2b4ea0, release build
Libraries:
wxWidgets 3.2.6
FreeType 2.13.3
HarfBuzz 10.0.1
FontConfig 2.15.0
libcurl/8.10.1-DEV Schannel zlib/1.3.1
Platform: Windows 11 (build 26100), 64-bit edition, 64 bit, Little endian, wxMSW
OpenGL: Intel, Intel(R) Iris(R) Xe Graphics, 4.6.0 - Build 31.0.101.5186
Build Info:
Date: Feb 5 2025 04:21:17
wxWidgets: 3.2.6 (wchar_t,wx containers)
Boost: 1.86.0
OCC: 7.8.1
Curl: 8.10.1-DEV
ngspice: 44
Compiler: Visual C++ 1942 without C++ ABI
Build settings:
I agree.
I also find the function entirely satisfactory.
I believe I would find having to tick a box generated by a programme, every time I joined or crossed two wires, extremely irritating.
I think a lot of PCB designers consider a schematic a necessary evil also.
At least speaking for myself, the schematic is how a circuit designer thinks. I cannot fathom the “necessary evil” description of a schematic diagram.
For me, this looks very much like the expected behavior.
That’s probably because you’re primarily a circuit designer. I know professional PCB layouters, who indeed view the schematic editor as “just that thing that I’m forced to use so I can generate netlist somehow”. In fact, one of them hates schematic capture so much he outsources it (it’s Orcad, so I don’t blame him). But, to be fair, I know only a handful of them.
Make them hot pink so they stand out.
Just repeating the OP’s term. A little piece of irony.
Personally, I think a well drawn schematic is a thing of beauty and a joy forever.
A scheme is very important for a project, yes. Who here designs a PCB without using a wiring diagram? And another thing, when you get used to drawing, or even redesigning a circuit to modify, when you make the change in the schematic and update the PCB, the connections will be returned to their actual places. It is also worth remembering the importance of the schematic design, as after a PCB is routed, the search for connections becomes complicated. Therefore, without a schematic, I believe that only small projects with few components are worth making the PCB without a schematic.
I tend to especially be annoyed by the autoconnect behaviour when dragging symbols with already connected wires in a schematic.
To me it would seem logical to not autoconnect in that case, and that the connections are made when drawing wires.
This get’s into my universally applicable method for eliminating paperwork: Print everything on stainless steel instead. Then it is steely or steelwork. Irony or ironwork might be OK but it is subject to rust.
Seriously though: To the designer the schematic is not just a netlist. If that were true, then any layout which agrees with the netlist would work OK. If I were to take a good schematic and drastically mis-arrange the symbols without changing the netlist connections, it would become a big “huh??” with as many questions as answers.