I was wondering if 35 mils is the smallest via size possible in KiCad? I checked the reference manual and they didn’t mention the minimum size or feature any via smaller than 45 mil. Seems kinda large considering pcb fabs offer plated throug hole vias at 8 mil
Actually, the very helpful user ChrisGammell supplied an answer to this some time ago, it can be found here: OSHPark PCB Rules He shows that you can edit the minimum hole dimensions under the global design rules. Thanks Chris!
If you do that, will all the smaller vias be flagged as design rule violations?
After changing the global rules, you can choose the size of your vias on the “net” (idk much about netlists in pcbnew) in the Net Class Editor (top menu bar: Design Rules > Design Rules > Net Class Editor tab). This menu won’t let you put in any dimensions that violate your global minimums, so there’s no way to put down any smaller via than the global min
As a side question, in my coplanar wave guide layout, the copper pour isn’t touching the vias. This is because of the 5 mil clearance I chose in the copper plane settings. Does any one know how to make an exception for these vias? I want the vias to connect the top copper planes to the backside ground plane
Here’s a pic of the issue: http://imgur.com/xEGj6ko
edit: It’s affecting my ground plane too : (
There’s no way to place vias that will connect to a fill without placing a track from something on the same net. e.g. run a track from a GND pad then place a via then a piece of track and then another via.
If you don’t do it this way then every time the board connectivity is updated (move/add parts, re-fill zones etc.) the vias will all become isolated as no-net vias which will never connect to fills.
There is a feature request for automatic via-stitching but it isn’t implemented yet.
To do this you need a netlist and something connected to the GND net (input/output connectors?)
Take a look at Via Stitching in PCBNEW for a video about this.
I see what you are saying. Well, I guess the only way to do this kind of thing is to link a netlist…I went ahead and read through the KiCad tutorial that shows how to link schematics to layouts, including the footprint selector. Actually, this tool is pretty great! And thanks for the video link too, that’s what I’m gonna try to accomplish now that I have valid net names to work with
So I think I’m close to figuring all of this out. Thanks a lot to the community on here, you guys are great. I’m trying to set up my top copper plane, and I want it to be of the “GND” net. However, whenever I assign it to GND and run the DRC, it doesn’t fill in the copper plane (and thus, no desired clearance shown away from other components). Here’s an image: http://imgur.com/NTqVPGk. When I change the copper plane settings so that it has no net (by selecting ) and then run the DRC, it gives me the pour I want - image: http://imgur.com/xHNzyKl. Anyone know how to get it to do the proper pour with a selected net?
“Copper islands” are automatically removed as they’re normally unwanted. A copper island is defined as any area of fill that isn’t attached electrically to anything.
So, to get a top-layer ground fill you need to have at least one pad or via on the top layer for the fill to join to. In a complete coplanar design you’ll normally have a connector or something at each end connecting to ground and then a row of vias alongside your controlled impedance trace that connects the two ground fills.
The logic is that a random piece of copper can’t be “GND” because it’s not GND until it’s connected to something that defines it as GND (e.g. a connector, a power regulator etc.)
The reason that the “no net” fill appears is because this is an exception, because it isn’t a normal net, connecting to nothing is by definition what it is meant to do. The only thing no-net copper is normally used for is copper layer graphics such as logos and product numbers.
You are absolutely right. As soon as I made the copper zone big enough to include some component at net GND, it worked the way I wanted it to. Thanks a lot!