I intend to do this and had some discussions with Fabien about it but have not gotten around to it.
Backported to 7.0 too:
Will you do this experiments on short notice?
Does is work or not?
It is advertized, but I do not see any examples. Who is responsible for this piece of code? People start asking, but as the simulator guy I am unable to answer any questions about IBIS.
IBIS in current 7.0.9 is broken.
A fix (IBIS simulations broken (#16223) · Issues · KiCad / KiCad Source Code / kicad · GitLab) has been uploaded to 7 bug fix repository (will be available in upcoming 7.0.10) and to current 7.99 nightlies (available now). Thanks to Keeth and Seth for such ultra-fast action!
With today’s nightly on MS Windows I have been able to run a demo (provided by Keeth).
IBIS.7z (11.8 KB)
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I have just had a look at the project you have offered for download.
If you want to simulate this astable oscillator, then the choice of an IBIS model for circuit simulation is the completely wrong choice!
Why?
The IBIS model does not describe the inner workings of an integrated circuit. IBIS models are made to describe the interfaces of ICs (output drivers, input receivers), but not the circuit functionality. They are made for specialists to simulate the high speed behavior of interconnects between integrated circuits (so called signal integrity).
For a simple circuit simulation (of the oscillator) you will need an ordinary spice model for the circuit. I don’t know if Nexperia has one, but TI does. After attaching the model, you have to select the proper pin sequence, as symbol and model pin numbers do not match.
In your circuit you have used a battery symbol. This is not a valid spice power supply. You should use a VDC symbol from Simulation_Spice library.
You have chosen a 1 Meg resistor to charge the capacitor. This is probably too large, compared to the input resistance of the Schmitt-Trigger. The capacitor might not charge fast enough…
With a 100k resistor and KiCad 7.99 I then have got
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There’s now an IBIS demo schematic in the nightlies.
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I signed up just to say thanks to the devs for introducing the IBIS model feature. Using the latest nightly, I was able to simulate a microstrip with the help of the Simulation SPICE > IBIS_DRIVER part, along with the Simulation SPICE > TLINE part.
The TLINE part in the library is not set-up to use the ngspice TLINE model. So I had to copy the TLINE part to a local library and edit its simulation model. It was no big deal.
The Transmission Lines page of the Calculator Tools made determining the TLINE parameters a breeze.
I’ve been waiting for decades for IBIS support in a low-cost/free CAD tool. This is awesome!
I’m not expecting super-accurate results, and won’t be designing PC motherboards with this, but it is a nice tool for verifying the effect of series termination on a high-speed digital signal. It also lets you simulate the various drive speeds of GPIO outputs to check that you meet the timing requirements of the connected device.
Now to figure out how I can simulate crosstalk with this new feature. Any ideas?
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I had more screenshots, but the forum won’t let me post more than one media item at a time.
Simulation of GPIO configured as medium speed, driving a 4cm-long 76Ohm microstrip via a 22Ohm series termination resistor, at 10MHz.
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Read this FAQ for posting information.
Open three more topics and read eleven posts and you will promote yourself to Basic.
Crosstalk is very dependent from the physical layout of the tracks. To simulate that you will need a field solver like OpenEMS. Apparently some people have success with this in combination with KiCad / FreeCAD, but it’s probably not very “integrated” yet.
But with your transmission line you already have a very similar problem. How do you verify that your nice looking model is close enough to your PCB properties to be useful?
Crosstalk is very dependent from the physical layout of the tracks. To simulate that you will need a field solver like OpenEMS.
I just need to determine the minimum separation between long-running parallel traces. What I’m looking for is pre-layout analysis tool like Hyperlynx.
From what I can tell, OpenEMS doesn’t understand IBIS, so I would have to first generate the driver output waveforms with (now) KiCAD or some other tool that understands IBIS. I would then have to manually “draw” the trace geometry with code.
But with your transmission line you already have a very similar problem. How do you verify that your nice looking model is close enough to your PCB properties to be useful?
I no longer have access to (expensive) commercial signal integrity tools, so I guess all I can do to is measure the waveform with the modest bandwidth oscilloscope that I have. My “nice looking model” at least gives me a rough idea.
I’m currently limited in the number of consecutive thread comments, so here is the continuation of my screenshots that I couldn’t post before…
The ringing is worse without the series termination resistor, as expected.
I should have picked a higher frequency and a longer transmission line to better showcase the utility of this sort of simulation.
In my particular case, I just wanted to check if series termination resistors would be worthwhile on an SPI bus running only a few inches. Plus I wanted to check what was the slowest GPIO speed I could get away with and still have a clean-looking waveform.
Thanks again to the devs for this wonderful feature!
ngspice offers a model for coupled transmission lines. Please have a look at chapter 6.4.2 Coupled Multiconductor Line (CPL) of the ngspice manual (Ngspice, the open source Spice circuit simulator - Documentation: manual and control flow).
I can imagine that you have for example two drivers, two receivers and two coupled transmission lines.
Unfortunately the description in the manual is too short and seems to be not aligned to the example netlist lines.
However there are some examples for using the CPL transmission lines in our example distribution at TM examples.
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For those wanting to model vias as very short transmission line segments, I discovered the Saturn PCB Toolkit that can calculate their impedance:
The transmission delay of vias is of course insignificant, but what may matter more is the impedance discontinuity causing reflections and degrading the signal.
This of course assumes the PCB trace references the same ground/power plane after switching layers. I don’t know how to model a change of reference plane; I don’t even know if it’s possible with lumped RLC components and transmission lines. It gets more complicated when you consider “stitching” vias/capacitors. This is why I like 6-layer PCB stackups (not considering their cost). 
Did you read my above comment?
Now, if you open two more different threads and read a total of five different posts in those threads, you will promote yourself to Basic, when you will then be able to post whatever in any volume. 
Yes, I read your above comment. I unfortunately don’t yet have anything else to discuss that’s worth opening two new threads. I’m still learning KiCAD, so I guess it won’t be long until I have some questions or suggestions. A lot of the questions I had along the way had already been answered either here or on other forums.
I suppose I should have started a new thread about my IBIS experimentation instead of hijacking this one (with my apologies to the OP).
Sorry, open means click on and read/look at a few posts.
Open doesn’t mean start new threads.
I appologise for the confusion.
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Hello to all,
I’m very sorry but in the mean time I completely forget to come here and see all you’re interesting replies. Wow ! I didn’t expect that
Many thanks to Holger, because I didn’t know that Ibis model describe only the interfaces of ICs
Very interesting !
Thanks a lot again and best regards to all,
Pascal