In your screenshots of the low-poly count circles, the GND plane between the via’s barely connects:
Whether it connects at all is of course a function of via diameter, via clearance, and distance between the via’s.
It is however also defined by the line widht that KiCad uses to draw the features on the GND plane, and in your screenshot that linewidth is apparently thicker then the available area, which results in the neck-down.
If this is a problem, it can be relatively easily fixed by giving the GND plane a little more room in that area. It can be done by either reducing the via size a tiny bit, or by reducing the clearance in the GND plane.
Also related to this:
KiCad does not support a “pad stack” as of yet. If you’re unfamiliar with the term: A “Pad stack” means that the form of a pad can be defined for each layer of a multi layer PCB separately. In KiCad upto version V5.1.x each THT pad (or via) has the same size on each layer of the PCB.
In KiCad-nightly V5.99 a first step into the direction of a pad stack is being implemented. While defining THT pads in the Footprint Editor, there is an option to remove the pad from layers on which there is no track connected:
In your case this would result in smaller holes in the GND plane because the via’s do not have pads on those layers.
— 8<------ 8<------ 8<------ 8<—
On a side note:
Are you familiar with techniques like micro via’s and “back drilling”?
Those may be important to you, depending on the frequency ranges you are interested in. My knowledge in this area is however extremely limited.
Paul, we mostly or totally agree, I have just communicated badly. You have pointed out the same things than I have. Where I was wrong was saying that gerber doesn’t have to way to reverse the file polarity. This is the relevant section 5.6.4 from the standard.
The .FilePolarity specifies whether the image represents thepresence or absenceof material. The .FilePolarity attribute does notchange the image - no attribute does. It changes the interpretation of the image. For example, in a copper layer in positive polarity a round flash generates a copper pad. In a copper layer in negative polarity it generates a clearance.
But as it says, it affects the interpretation of the file. It’s not possible to change that from KiCad, and if there were, it wouldn’t affect file size in itself (which was the important thing for the topic at hand, and which the original poster asked about).
We both noticed that item polarity can be changed according to the standard (the official name is “clear” and “dark” polarity); section 2.7. We both also said it would be the most effective way to represent via clearances, but KiCad doesn’t do that.
I also noted that in my posts, and it may indeed be important because it adds four lines for each via. However,
If the new zone filling algorithm is used – which should be used to reduce the file size – there is no “line width” for drawing. The old algo actually used segments (draw objects) for drawing polygon outlines, as can be seen in my post above with several screenshots. The new algo has just minimum width, but I think this may have caused bugs where the minimum width isn’t obeyed (https://gitlab.com/kicad/code/kicad/-/issues/7162, https://gitlab.com/kicad/code/kicad/-/issues/6907).
It’s important to check the minimum width in the zone properties and if the detail pointed out by Paul breaks it. If it’s wrong it would be important to add a use case into a bug report or create a new one.
Yeah Gentlemen,
I am till having issues… but hopefully after some putzing around I will be able to get something workable out of this. Will report back once the order is placed…!
That is for sure a problem.
Smaller vias will not be up to the engineering good practices guidelines that my engineer has suggested… we’ll see. I will further reduce clearance in the GND planes. That is pretty safe, down to 80 microns it is totally game.
It can be any of a number of clearance values.
Clearances may overlap, but they are regarded as minimum distances to other copper items, so the component which has the largest clearance set defines the width of the gap.
The normal way is to define clearance values in the net classes, and assign all nets to some defined Net Class. Nets that have not been assigned to a specific Net Class are in the Default Net Class.
Tracks and Vias always have the Clearance of the net that they belong to. Pads and zones inherit the clearance value from the net class they are assigned to. You can overrule this default behavior by manually setting a clearance value for a pad to a specific value.
Just last day I had an excellent example of this. Another Forum user had some trouble with a small SMT part to which a fat track with a large clearance had to be connected. I was in a good mood, and needed to refresh my memory, so I made an example out of it, made some notes and posted it all here on the forum:
Oops, forgot to add:
You can make the clearances visible with: Pcbnew / Preferences / Preferences / Pcbnew / Display Options / Clearance Outlines
Also, KiCad does not calculate zone boundaries automatically, you have to manually trigger the re-calculation of the boundaries with the b shortcut key, or Right click on a zone and then select Zones / Fill
that my engineer has suggested… we’ll see. I will further reduce clearance in the GND planes. That is pretty safe, down to 80 microns it is totally game.
