Thank you so much!
Ok. Returning to the OP, how do I make the “negative” from my ground planes?
Again, I am a newbie, so a level of elaboration will be appreciated 
That’s not possible in KiCad. Using negative plotting for gerbers isn’t a standard way to do anything, there may have been historical practical reasons to do that but not nowadays, and KiCad doesn’t support it. In any case it wouldn’t help if negative plotting would only reverse the “color” of the items because there would be the same amount of data.
If reducing the amount of data by using the new zone filling algorithm and simplifying the arc approximation didn’t help, I don’t think there’s anything else KiCad can do for you. KiCad export algorithms should be radically changed first to handle round holes in filled areas as flashes, or to draw them with arcs instead of segments.
But I’m still interested about the problem and possible solutions. However, you still haven’t provided much information.
- How small you need the files to be (and why)?
- How large/small they get with different arc approximation values and zone filling strategy (in 5.99)?
- Can you still show a screenshot from gerbview where I can see the internals of the gerber file? Like my screenshots where the wireframes were visible?
- Do you insist having negative gerbers only because of this file size problem?
Thank you @eelik!
- We would like files to be reasonably versatile so that the PCB manufacturer could actually open and check them. At this point, 180 Mb Gerber for one GND plane is a bit much;
- I have been able to get it down to 100 Mb already using your hints, and still working on it. There is hope;
- Will post here in reply as well once I get the most recent fill completed… it takes couple of hours. I am not entirely sure what you mean by “internals” - actual text of the Gerber commands snippet? I will add some more screen shots soon;
- Yes, size is the main problem.
I’m not entirely sure, but I do think that “negative Gerbers” is a part of the Gerber specification itself.
As written before in this thread, it is used for the solder mask layer, where cutouts are made in a sheet.
This is also not true:
With negative gerbers, you can define an aperture, and then “flash” it as a round hole on each via location. Now each hole is 8 straight segments.
I do agree that it’s not supported by KiCad. Just maybe you can (ab-) use the solder mask layer and convince your PCB manufacturer to plot it as a negative copper layer.
But it’s outside of KiCad’s normal work flow and you’re on your own in doing so.
I mean the “wireframe” like in the screenshot in my post above. Is it the simplest possible? If it is, there’s hardly a way to make the file any smaller.
In the end it boils down to “gerber code for one via” 115000 times. If one via takes, say, 250 bytes, it will be about 30 megabytes. That doesn’t include the overhead of everything else in the file. If you want to know the details:
- Vias themselves are flashed, one via takes one gerber line:
X173800000Y-86100000D03* - If you have so coarse zone filling that the clearance hole is an octagon, it takes basically 10 similar lines, 8 for the octagon and 2 extra for connecting the polygon hole to the rest of the polygon.
It’s even theoretically impossible to go below that with the current gerber generation algorithm. The only way by changing the algorith would be to replace the 8 octagon lines with one arc (which is basically covered by the wishlist issue above). Even using circular apertures with “clear” polarity for clearance holes wouldn’t then help much more.
We are talking about two different things. “Clear” polarity is a way to take off from an item flashed with the default dark polarity, as you say. “Negative” in the export dialog means negative colors, and likewise in the “negative gerber”. Basically a “negative layer” could be done using different algorithm, thus saving bytes. But it would be easier and better to create normal layers with different algorithm.
I don’t see how the mask layer “negativity” would be relevant. It’s created with the same algorithms. Graphics in the layer is graphics in the gerber, it’s not reversed. The “negative” comes in interpetation when it’s compared with the physical board.
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@paulvdh @eelik Thank you Gentlemen,
I think at least I’ve got this down to some manageable / open-able condition. The GNDs are identical so I am only sending one to the PCB manufacturer. They are 128Mb and open quite okay in Gerbview. I really appreciate your help and discussion, your hints has helped me to optimize the settings to a plausible outcome (TBD, submitted to review now :))
I’m really curious, what is that supposed to be? Some sort of antenna? Capacitance matrix? EM field detector?
Right you are @qu1ck!
It is a radiation detector array for proton cancer radiotherapy.
… hopefully it will be able to make it more affordable…!
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This is mostly theoretical, as KiCad does not support arbitrary “negatively defined” items to be defined by their users. It’s just some stubborn misconception.
First:
I had a look at the (unofficial source) https://www2.pv.infn.it/~servel/rc_images/gerber_rs274xrevd_e.pdf
And from that file:
Extended Gerber Format, which is also called RS-274X, provides enhancements that handle polygon fill codes, positive/negative image compositing, and custom apertures,
So it does support negative features, and apparently does so in several ways for different sorts of features (flash codes, whole images). In the header(line 6) of the solder mask file I used below is a line that (probably) specifies the whole file is to be inverted:
%TF.FilePolarity,Negative*%
Sure, if you just define gerbers as being “negative”, then file size does not change. However, the idea about the ability to use negative features in Gerber results in being able to draw the things that are not in the output, instead of drawing the image itself.
Have a look at this part of a gerber file generated by KiCad:
It shows some defined apertures, which are then flashed on the solder mask.
First the apertures are defined, and after that each hole in the soldermask is just a single line in the Gerber file. Below is a small excerpt of the Gerber file, First is specified that aperture “D30” is being selected, and then a list of coordinates on which locations that aperture is to be flashed.
D30*
X137160000Y-96520000D03*
X139700000Y-96520000D03*
X142240000Y-96520000D03*
X144780000Y-96520000D03*
X147320000Y-96520000D03*
X149860000Y-96520000D03*
X137160000Y-99060000D03*
Now compare that with the gerber for the orange GND plane in Gramotey’s screenshot:
For each hole in the GND plane, the GND plane is directed around each via with a low poly approximation of a circle. In this case each hole is constructed out of 10 straight line segments, and thus 10 lines of Gerber code.
If it were possible to use the negative gerbers in the GND plane just as in the solder mask, then each group of 10 line segments could be replaced by one aperture flash. This will result in a reduction of filesize of 90% for all the via holes. And for 115000 holes that would save more then a million lines in the gerber file.
If file size is that important then you could hack into the files, either with a text editor or by writing a script, and then remove a lot of the internal structure of the GND plane, and replace it with the negatively defined features such as in the solder mask layer.
Normally via’s are covered by solder mask and therefore not in the solder mask layer, but probably are if you turn of the “tented via” option during gerber creation.
In your screenshots of the low-poly count circles, the GND plane between the via’s barely connects:
Whether it connects at all is of course a function of via diameter, via clearance, and distance between the via’s.
It is however also defined by the line widht that KiCad uses to draw the features on the GND plane, and in your screenshot that linewidth is apparently thicker then the available area, which results in the neck-down.
If this is a problem, it can be relatively easily fixed by giving the GND plane a little more room in that area. It can be done by either reducing the via size a tiny bit, or by reducing the clearance in the GND plane.
Also related to this:
KiCad does not support a “pad stack” as of yet. If you’re unfamiliar with the term: A “Pad stack” means that the form of a pad can be defined for each layer of a multi layer PCB separately. In KiCad upto version V5.1.x each THT pad (or via) has the same size on each layer of the PCB.
In KiCad-nightly V5.99 a first step into the direction of a pad stack is being implemented. While defining THT pads in the Footprint Editor, there is an option to remove the pad from layers on which there is no track connected:
In your case this would result in smaller holes in the GND plane because the via’s do not have pads on those layers.
— 8<------ 8<------ 8<------ 8<—
On a side note:
Are you familiar with techniques like micro via’s and “back drilling”?
Those may be important to you, depending on the frequency ranges you are interested in. My knowledge in this area is however extremely limited.
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Paul, we mostly or totally agree, I have just communicated badly. You have pointed out the same things than I have. Where I was wrong was saying that gerber doesn’t have to way to reverse the file polarity. This is the relevant section 5.6.4 from the standard.
The .FilePolarity specifies whether the image represents thepresence or absenceof material. The .FilePolarity attribute does notchange the image - no attribute does. It changes the interpretation of the image. For example, in a copper layer in positive polarity a round flash generates a copper pad. In a copper layer in negative polarity it generates a clearance.
But as it says, it affects the interpretation of the file. It’s not possible to change that from KiCad, and if there were, it wouldn’t affect file size in itself (which was the important thing for the topic at hand, and which the original poster asked about).
We both noticed that item polarity can be changed according to the standard (the official name is “clear” and “dark” polarity); section 2.7. We both also said it would be the most effective way to represent via clearances, but KiCad doesn’t do that.
I also noted that in my posts, and it may indeed be important because it adds four lines for each via. However,
If the new zone filling algorithm is used – which should be used to reduce the file size – there is no “line width” for drawing. The old algo actually used segments (draw objects) for drawing polygon outlines, as can be seen in my post above with several screenshots. The new algo has just minimum width, but I think this may have caused bugs where the minimum width isn’t obeyed (https://gitlab.com/kicad/code/kicad/-/issues/7162, https://gitlab.com/kicad/code/kicad/-/issues/6907).
It’s important to check the minimum width in the zone properties and if the detail pointed out by Paul breaks it. If it’s wrong it would be important to add a use case into a bug report or create a new one.
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Yeah Gentlemen,
I am till having issues… but hopefully after some putzing around I will be able to get something workable out of this. Will report back once the order is placed…!
That is for sure a problem.
Smaller vias will not be up to the engineering good practices guidelines that my engineer has suggested… we’ll see. I will further reduce clearance in the GND planes. That is pretty safe, down to 80 microns it is totally game.
I’m still interested: what is the zone minimum width, and how wide is that “neckdown” in the narrowest spot?
But what is the value of Min. width in the zone’s properties?
It was 0.12 and when I reduced it did not fill anything at all.
But what controls the ‘stand-off’ distance from the vias?
It can be any of a number of clearance values.
Clearances may overlap, but they are regarded as minimum distances to other copper items, so the component which has the largest clearance set defines the width of the gap.
The normal way is to define clearance values in the net classes, and assign all nets to some defined Net Class. Nets that have not been assigned to a specific Net Class are in the Default Net Class.
Tracks and Vias always have the Clearance of the net that they belong to. Pads and zones inherit the clearance value from the net class they are assigned to. You can overrule this default behavior by manually setting a clearance value for a pad to a specific value.
Just last day I had an excellent example of this. Another Forum user had some trouble with a small SMT part to which a fat track with a large clearance had to be connected. I was in a good mood, and needed to refresh my memory, so I made an example out of it, made some notes and posted it all here on the forum:
Oops, forgot to add:
You can make the clearances visible with: Pcbnew / Preferences / Preferences / Pcbnew / Display Options / Clearance Outlines
Also, KiCad does not calculate zone boundaries automatically, you have to manually trigger the re-calculation of the boundaries with the b shortcut key, or Right click on a zone and then select Zones / Fill
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