How to Handle Component References for SMD boards

[pmi]

This is my first foray into a SMD layout and I am not sure what to do with the component references. My circuit uses a MAX17320 (24 pin TQFN package), and I am modelling my layout on the MAX17320S Evaluation Board. I have all the components close to the chip, but the component references fail the DRC rules I set up based on the JCLPCB specifies for a 4 layer board.

If I make the font smaller, it will probably be illegible on the board or it will violate the JCLPCB design rules for size. Not sure how to proceed.

[eelik]

Are you willing/can you share the design file here?

[paulvdh]

Is this for DRC violations because of overlapping silkscreen items?
To me it already looks quite good, There are only a few texts which overlap, and those are mostly in an area where you still have some room (such as C423 and U402).

Sometimes the References are grouped together with the same relative locations as the footprints, but doing that here does not look like a good option.

[greg_m]

On dense boards I just place major components references, ICs, connectors, etc. For everything else (passive components) I have documentation with drawings.

[pmi]

JLCPCB has these rules for the silkscreen

Pad to Silkscreen 0.15mm
Min Text Height 1.0mm
Min Line Width 0.153 mm
Character width:height 1:6

I am violating one or more is several places. I have been moving the references around as I get these errors, but it is a bit like Whack-A-Mole…fix one and another pops up…lol

My question was a bit more general as to what do people do when the DRC complains about the silkscreen and the layout is tight? I assume layout trumps reference placement, but the references have to be on the board. Or, do I move the components to make the references fit?

[paulvdh]

Footprint placement and tracks are mandatory for a working PCB, while Silkscreen is optional. With current (nearly) fully automated assembly, Silkscreen is mostly useful for rework and repair. Repair of PCB’s is also getting less common for many years, and there are also tools like Interactive HTML Bom and Board View.

KiCad does have a setting for: PCB Editor / File / Board Setup / Design Rules / Constraints / Silkscreen / Minimum item Clearance, but I am not sure of what items it calculates a clearance from.

Most PCB manufacturers automatically subtract the solder mask layer from the silkscreen, with as a result that silkscreen text is never printed over pads, but there is no guarantee for this. KiCad also has an option to do this during gerber file creation, and then you can observe the results before sending the files to a fab.

But for the rest, I guess it’s mostly you do you best but there are limits. If some texts are missing or not readable, then it’s not such a big issue, as long as text is not printed over pads, because then you can’t solder properly anymore.

[eelik]

@pmi

I assume layout trumps reference placement

Yes, but not all components are critical at all for positioning.

@pmi

but the references have to be on the board

Says who? If you do this for work and someone else has to read the board, then it’s possible that they are mandatory (if the size and the component density of the board allows). Otherwise you are free to choose.

@pmi

JLCPCB has these rules for the silkscreen

Silkscreen isn’t usually critical, and the manufacturers won’t complain if the text isn’t fully readable everywhere. I would say 0.8 mm height is still OK (IIRC I have used even 0.7 with JLCPCB and the text was decipherable). “Width:height” means actually line width (KiCad “thickness”, not character width. In KiCad you can set character width the same or a bit smaller than height. Narrower text may give you a bit more space.

Also the silk/pad clearance sounds a bit exaggerated, although it’s more important than legibility.

For silk editing for the whole board I use certain Appearance settings. For top layer,

• F.Mask
• F.Silkscreen
• Edge.Cuts
• (Objects → ) Vias
• Footprints
• Pads
• Footprint text
• Texts
  are visible. Other layers than those three are not visible.

In the Selection filter only Text is active. This makes moving the reference designators very easy.

Now it’s easy to see only the relevant information for positioning the reference designators. This works for most cases because usually you don’t have to see any copper, not even pads. The mask openings cover the pads and the silk must avoid those mask openings. If the footprints have high quality silk markings, you can also see or imagine the component outlines there (roughly).

Note that for legibility you should avoid placing a silkcreen character’s line right on a via hole. That’s why I make vias visible. Sometimes I even position a character’s middle opening, like the center of 0, U, C etc., directly on a via hole so that the via doesn’t cut the character’s line.

I also use the 3D view. It gives another “opinion” to understand what the final board will look like. Because it’s more realistic, it may be easier to see problems – or non-problems – with the silk markings.

[3Dogs]

Your silkscreen characters look huge to me. I often use text that is less than 1/2 that size, and it’s perfectly legible.

There are other tricks you can use, if there is simply no place to put a reference.

1. Use a “call out” line - put the text where it will fit, and then draw a line to the component.
2. As was mentioned earlier, you can stack the refs in the same order as the components, and put them off to the side.
3. Use a single character (“A”) and then put a table that cross-references “A” to “R416"

[johanh]

@eelik

Silkscreen isn’t usually critical, and the manufacturers won’t complain if the text isn’t fully readable everywhere. I would say 0.8 mm height is still OK (IIRC I have used even 0.7 with JLCPCB and the text was decipherable).

Agree, the JLCPCB 1.0 mm text size is not a hard limit. I.e. they won’t notify you if you break this rule. I’ve used 0.8 mm without problems.

[RaptorUK]

@3Dogs

Use a “call out” line -

Yup, and make the text smaller, a little . . .

[Piotr]

@pmi

but the references have to be on the board.

I don’t remember ever (since 90s) having references on the board.
Using Protel 3 for long time we used its silkscreen layer (have the advantage of following footprint when flipped top/bottom) for our documentation so we didn’t had it on PCB. When we needed to use silkscreen layer it was only for text for user like terminal block pin description (texts of kind: “GND” “+12V”, “IN1”, “IN2” and so on). In such case I placed those texts on one graphic layer and sending PCB to manufacture informed them to use this layer as silkscreen.
When moved to KiCad in 2017 I found the other layer pair swapping layer with footprints (courtyard) and used it for documentation so now our PCB have silkscreen but containing only rectangles around footprints. I have references and values at courtyard layers to have them in our documentation.
How I place references you can see here:

Creating my first footprint: questions as a beginner

I’m trying to stick to that but as Kicad is not allowing me to have 1 symbol mapped to 2 footprints, You don’t understand. If your element has two connectors but not at cables but at its PCB then they both are ‘one insertion’ so one footprint. I started to assemble SMD myself around 1992 and till now I don’t have microscope. When I started to have to use glasses for reading I have bought a workshop lamp with magnifying glass. I have no space at desk for station so I use: Not needed. I…

[pmi]

The text is the min allowed height of 1 mm. Thanks for the reference label tips.

[3Dogs]

It’s unlikely that they will refuse to manufacture your boards if the silkscreen text is less than 1mm - they just won’t guarantee legibility.

[mike_redant]

I happily use 0.6mm high component designator text size and JLCPCB just go ahead with it

On this PCB, the word “Engineering” is less than 0.5mm in height. It’s a crap photo, but if I magnify the actual silkscreen it’s is just legible.

[davidsrsb]

SMD 0402 is a struggle to fit a silkscreen, 0201 and even 01005 make it a hopeless task to show references on the board. Why we have Fab layers.