How to design Castellated Pins

I have searched this forum and other places as well trying to understand how to properly design Castellated pins in KiCad but I have not been able to find a good solution.
I don’t want to places via all other the edge of the PCB, to me a better solution would be to have a proper footprint for this and that is what I am trying to do.

See the image below, the hole size and distance is designed according to my fab-house specification, it is placed on the edge of the PCB and edge dimension goes right through the middle of the holes.

Now the problem is that I can not connect to those pins anymore. I guess that is because they are considered to be outside the boarder of the PCB. How can that be changed?

Some older questions mention changing the shape offset of the pin but for me changing that has no effect. Other solutions suggest that you should route track to these pins (instead of trying to route tracks from them) but that has no effect for me either. (I am trying to connect copper zones to them)

So please suggest what I can try instead. Any answer would be helpful as I am giving up hopes here.

Here is my KiCad PCBnew version information:

Application: Pcbnew
Version: (5.1.6)-1, release build
wxWidgets 3.0.4
libcurl/7.66.0 OpenSSL/1.1.1d (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.1.1) nghttp2/1.39.2
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8)
Boost: 1.71.0
OpenCASCADE Community Edition: 6.9.1
Curl: 7.66.0
Compiler: GCC 9.2.0 with C++ ABI 1013

Build settings:

Yes castelated pins are not possible without setting “allow DRC violations”. Simply because they are not part of the official feature set so what you do is really a workaround and workarounds come with certain restrictions. (The reason is that since version 5 the edge cut layer is checked by DRC. So you can not have a trace too close to the edge cut without a DRC violation.)

Another workaround is to make a complex pad shape that already includes part of the trace. This is however quite inflexible so i personally would just live with the DRC violation here.

@Rene_Poschl, thansk for the quick response.
The only place I have found to disable DRC is in Route -> Interactive Router settings -> Setting Mode to “Highlight Collision”, I have checked “Allow DRC violations”.
But when pouring copper it still does not connect to the pins placed on the edge.

We join the round pin to the zone with a track as wide as the pin. And live with the DRC error.

1 Like

My first idea would be to make Edge.Cuts bigger and draw true Edge cuts at some other layer (may be one of Eco layers) and send this layer gerber to factory as Edge.Cuts.

1 Like

1: You need wider copper pad towards the trace anyways. Can you rotate the pad 180 degrees?

That alone doesn’t solve the DRC problem yet. Contrary to what others say, it’s possible to make it without DRC errors. See SMD PCB Modules Kicad tutorial? and forward.

I kind of hinted at this solution with my mention of the option of making more complex pads :wink:

I just did not know that there is a detailed explanation out there already that can be easily linked :slight_smile: I am however uncertain what would happen on a multi layer board with your solution as the THT pad surely violates the minimum restring on inner layers.

If you are motivated then you could make a FAQ article out of your post(s) or possibly also just adding another entry to the “how to make a footprint” tutorial (as a new answer to that post). Could even be just a link at the end of that tutorial to the old thread.

Good reminder. Full padstack will probably help, but not until it’s implemented in KiCad.

I was thinking about that, the question pops up every now and then. Maybe I’ll do some more exprimentation and write something.

1 Like


I read the link you are referring too, I updated my castellated footprint to use your proposed solution (with 2 SMD pads and a hole instead).

(module Castellated_1 (layer F.Cu) (tedit 5AD72F4C)
  (fp_text reference REF** (at -0.05 2) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
  (fp_text value Castellated_1_0.6mmHole (at 0.05 -1.4) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
  (pad 1 thru_hole circle (at 0 0) (size 0.6001 0.6001) (drill 0.6) (layers *.Cu)
(clearance 0.001))
  (pad 1 smd rect (at 0 0.225) (size 1 0.45) (layers F.Cu F.Mask))
  (pad 1 smd rect (at 0.002508 0.37373) (size 1 0.75) (layers B.Cu B.Mask))
  (pad 1 smd roundrect (at 0 0.44958) (size 1 0.2) (layers F.Cu F.Mask)(roundrect_rratio 0.5))

It looked promising and as you have mentioned, the DRC passed successfully. Also the pads can be routed to properly but the DRC is now complaining about another issue now:

“Track too close to board edge”. Is there a solution for that?

In my solution there are two SMD pad in the front layer. You could make the one around the drill hole longer and move the smaller one farther from the hole, if you just have space on your board. The problem comes from the generic copper/edge clearance constraint: it doesn’t complain about pads, but it doesn’t allow traces or zone fills. Your traces are so thick that the round end of a trace goes too close to the edge.

BTW, attaching wide copper makes the module difficult to solder manually, just like with THT component pads. Thermal gap might be considered anyways, so you could narrow down the traces which connect to the castellated pads. Or use zones with thermal connections.

I have not tried to solder our castellated board manually so I cannot disagree with you in this point.

Our boards are working very well with oven soldering. And we have zones connecting every single castellated pad on one or more of the 4 layers.

We tried a solution similar to the one @Rene_Poschl proposed. But as the pads do not support copper on the inner layers, we made all conections by adding zones around the pads. Quite similar as the picture from @Alborz

The first part of the FAQ article is ready: Castellated edge; plated half holes in board edge. I think comments can be accepted here because it’s on topic and the original poster already got answers.

@eelik Looking forward to the FAQ. This topic had always bothered me in KiCad.
By the way I understand that soldering to those castellated pad with large traces going will be difficult but I though it was common practice to do the trace as big as the hole for castellated pads.

Mostly it’s the GND or other large zone which may make it difficult because it sucks the heat. Especially if both the castellated and the "mother"board have planes in the same pad. And the soldering iron power affects it, too. YMMV.

Useful FAQ.
However, I saw one error. The FAQ states that there is no support for castellated holes in Gerber, whereas they are perfectly supported. There is even a dedicated attribute to identify castellated holes and pads.

Thanks Frederik. I believe it’s only in the newer (latest) standard, X2 in the KiCad plot dialog. I just heard that fabrication attributes have been added to KiCad 5.99 and jpcharras now enabled them by default when I asked about castellation support in the mailing list.

Unfortunately these gerber extensions are hardly supported by any cheap manufacturers. In any case the castellation is made in the same way. I’ll update the FAQ article later.

It is indeed all very recent, and in all probability what you wrote was right at the time you wrote it.
I was told the cheap Chinese prototype fabricators are in the process of updating their software to take advantage of the X2 fabrication data.