If I change the B.Cu GND pour to Solid Pad connections I get this:
Capping is expensive.
Using a 0.6mm pad, 0.3mm hole for thermal vias is within budget Fabs capabilities and steals far less solder than the rather coarse KiCad default of 0.8/0.4
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Some regular suppliers like JLCPCB go down to vias with a 0.2mm hole
Obviously for solder theft, the smaller the hole the better.
Check your preferred supplier capabilities.
To address the original issue: Looks like the vias (which are actually PTHs) aren’t set to GND.
Why don’t connect pin 9 to GND in the schematic, BTW?
I had tried setting each thermal via pin to GND and it made no difference. What’s a PTH?
You didn’t showed yet what are thats vias Local Clearance and Settings.
Added later:
It looks they are not connected to GND or have some settings not allowing for being connected.
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PTH = plated through-hole (basically a regular component hole because KiCad doesn’t allow vias in footprints).
The pad properties screenshot above shows that that particular hole isn’t assigned to GND and the copper plane’s shape above that one suggests that the hole clearance is the issue.
I had the same problems, I solved changing the local clearance from the footprint, take a look at this thread:
I hope it helps !
It seems that setting the PTH and the top thermal pad to GND worked. I swear I had already tried this!
Note that your first screenshot just has “9” on the center pad, while your last post also has the “GND” net label attached.
People do silly things all the time. For example adding pad “8” to the GND net and then hitting escape instead of confirming, or adding it in the schematic, but then not syncing the netlist with the PCB ( With [F8])
Also, you have a big fat via right through pad nr 7 in the last screenshot. This does not matter much for hand soldering, but when using a solder stencil, then most of the solder will wick into the via hole and thereofore it is not recommended to put via’s through pads.
Also for the amount of solder for the themal pads. You have to balance the cutout in your solder stencil to match with the amount of solder that will wick into the via’s.
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Thanks! I was only messing around putting vias through pads.
How do I work out solder mask opening to allow for wicking?
Do you mean the back side of those 6 THT pad thermal pad holes in the screenshot above? Open Pad Properties and there are the layers to be toggled on/off. They probably have B.Mask off now.
Just an orthogonal reply…
Do you really need/want “via in pad” ?
True “via in pad” involves discussions with the fab house to fill the associated vias with epoxy to mitigate wicking. Additional expense
“Via in pad” involves well… Vias in the pad and can Introduce additional cost as the fab hous has to make sure the pad is level post drilling and plating
A third option exists, if viable. Remove the vias on the pad and use a larger copper fill to connect to it. Use vias in this area (outside the part) to take the heat away
You no longer have additonal fab cost nor concern about wicking and you have a nice bit of copper to heat up if you need to remove the part
Downside… Not the datasheet footprint and it could compromise tracking.
I was just using the standard footprint for the part. I will look at removing the via’s and using a larger ground plane with via’s outside the pad area.
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Yeah, I was having trouble with an assembly house because their board fab wanted to clip the silkscreen for a large diameter around vias and parts to the point it was compromising readability. They were concerned with covering the vias (tented vias) causing problems in assembly. Filling the vias is ok, covering them with trapped air and moisture inside is not. house After discussing it with the board house we came to an agreement to not clip the silkscreen so badly.
The point is any assembly house is going to resist assembling a board with tented vias. If you are soldering at home, no problem.
@ilium007 Have you made sure that pin 9 is attached to GND in your schematic? Sometimes I will use schematic symbol that doesn’t have the thermal pad of the footprint I have chosen called out. You may have to tweak your schematic symbol to make sure Pcbnew knows that pad 9 is connected to GND. Some parts will have an SOIC-8 without a thermal pad, but their smaller package footprints do have a pad.
All working now, thanks everyone!
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