I put a GND pour on the back of the board but the back copper pad that’s part of the footprint is unable to be connected to the GND layer even if I set the pad to the GND net. The TI datasheet for the LMR16030 says that the thermal vias need to be connected to a GND plane.
I am also a bit confused about solder wicking. A few posts I have read say that you need to be careful of the solder wicking down the via to the back leaving no solder under the TI PowerPad.
I have been playing around with it some more and I think this has to do with the copper pour keep out area, in this case I want zero keep out, I want the GND copper pour to join this component pad.
What are the settings for the zone on the B.Cu layer? What type of connection is specified in the zone configuration window ?
You can have the vias capped if you are having this assembled or put some kapton tape over the bottom layer prior to reflow if you are assembling it yourself.
Capping is expensive.
Using a 0.6mm pad, 0.3mm hole for thermal vias is within budget Fabs capabilities and steals far less solder than the rather coarse KiCad default of 0.8/0.4
Some regular suppliers like JLCPCB go down to vias with a 0.2mm hole
Obviously for solder theft, the smaller the hole the better.
Check your preferred supplier capabilities.
You didn’t showed yet what are thats vias Local Clearance and Settings.
Added later:
It looks they are not connected to GND or have some settings not allowing for being connected.
PTH = plated through-hole (basically a regular component hole because KiCad doesn’t allow vias in footprints).
The pad properties screenshot above shows that that particular hole isn’t assigned to GND and the copper plane’s shape above that one suggests that the hole clearance is the issue.
Note that your first screenshot just has “9” on the center pad, while your last post also has the “GND” net label attached.
People do silly things all the time. For example adding pad “8” to the GND net and then hitting escape instead of confirming, or adding it in the schematic, but then not syncing the netlist with the PCB ( With [F8])
Also, you have a big fat via right through pad nr 7 in the last screenshot. This does not matter much for hand soldering, but when using a solder stencil, then most of the solder will wick into the via hole and thereofore it is not recommended to put via’s through pads.
Also for the amount of solder for the themal pads. You have to balance the cutout in your solder stencil to match with the amount of solder that will wick into the via’s.
Do you mean the back side of those 6 THT pad thermal pad holes in the screenshot above? Open Pad Properties and there are the layers to be toggled on/off. They probably have B.Mask off now.
Just an orthogonal reply…
Do you really need/want “via in pad” ?
True “via in pad” involves discussions with the fab house to fill the associated vias with epoxy to mitigate wicking. Additional expense
“Via in pad” involves well… Vias in the pad and can Introduce additional cost as the fab hous has to make sure the pad is level post drilling and plating
A third option exists, if viable. Remove the vias on the pad and use a larger copper fill to connect to it. Use vias in this area (outside the part) to take the heat away
You no longer have additonal fab cost nor concern about wicking and you have a nice bit of copper to heat up if you need to remove the part
Downside… Not the datasheet footprint and it could compromise tracking.
I was just using the standard footprint for the part. I will look at removing the via’s and using a larger ground plane with via’s outside the pad area.
