I make the following circuit:
but I cannot start the simulator , see error message:
No compatibility mode selected!
warning, can’t find model tr_neg
warning, can’t find model tr_negbar
warning, can’t find model trigger
warning, can’t find model clear
warning, can’t find model reset
warning, model type mismatch in line
uoutputs jkff(1) vdd vss d_cd4098b_outputs io_4000b io_level={io_level} mntymxdly={mntymxdly}
warning, can’t find model trigger
warning, can’t find model trigdly
warning, can’t find model trigx
warning, can’t find model trigx_bar
warning, can’t find model trigx_barbar
warning, can’t find model trigdly
warning, can’t find model trigger
warning, can’t find model trig_0
warning, can’t find model trig_0
warning, can’t find model trigpreset
warning, can’t find model net-r2-pad2
warning, can’t find model net-r7-pad2
warning, can’t find model r
Circuit: KiCad schematic
Too many parameters for subcircuit type “cd4098b” (instance: xxu1)
Error: there aren’t any circuits loaded.
Spice Netlist
.include "/Users/max/Txt/WiperLand/rev2.0/WiperLand2/1_shot.lib"
.include "/Users/max/Txt/WiperLand/rev2.0/WiperLand2/BD675A.LIB"
XU1 GND Net-_C3-Pad1_ Net-_C2-Pad1_ Net-_C4-Pad2_ Net-_C5-Pad2_ Net-_U1-Pad11_ NC_01 GND Net-_R9-Pad2_ Net-_C5-Pad1_ Net-_U1-Pad11_ GND Net-_C2-Pad1_ Net-_C6-Pad1_ GND VCC CD4098B
C4 Net-_C2-Pad1_ Net-_C4-Pad2_ 100n
R4 Net-_C4-Pad2_ GND 10K
R6 Net-_C2-Pad1_ GND 100K
C2 Net-_C2-Pad1_ GND 100n
R2 VCC Net-_R2-Pad2_ Net-_R2-Pad2_ 1M
R3 Net-_R2-Pad2_ Net-_C3-Pad1_ 100K
C3 Net-_C3-Pad1_ GND 10u
R5 VCC Net-_C5-Pad2_ 100K
C5 Net-_C5-Pad1_ Net-_C5-Pad2_ 100n
R8 Net-_R7-Pad2_ Net-_C6-Pad1_ 100K
C6 Net-_C6-Pad1_ GND 10m
R7 VCC Net-_R7-Pad2_ Net-_R7-Pad2_ 1M
R9 Net-_Q1-Pad1_ Net-_R9-Pad2_ 4.7K
XQ1 Net-_Q1-Pad1_ /Vout GND bd675a
V1 VCC GND DC 12
R10 VCC /Vout R
( changed @ with # otherwise I cannot post )
.save #c4[i]
.save #r4[i]
.save #r6[i]
.save #c2[i]
.save #r2[i]
.save #r3[i]
.save #c3[i]
.save #r5[i]
.save #c5[i]
.save #r8[i]
.save #c6[i]
.save #r7[i]
.save #r9[i]
.save #v1[i]
.save #r10[i]
.save V(/Vout)
.save V(Net-_C2-Pad1_)
.save V(Net-_C3-Pad1_)
.save V(Net-_C4-Pad2_)
.save V(Net-_C5-Pad1_)
.save V(Net-_C5-Pad2_)
.save V(Net-_C6-Pad1_)
.save V(Net-_Q1-Pad1_)
.save V(Net-_R2-Pad2_)
.save V(Net-_R7-Pad2_)
.save V(Net-_R9-Pad2_)
.save V(Net-_U1-Pad11_)
.save V(Net-_U1-Pad7_)
.save V(VCC)
.tran 10m 10 0 10m uic
.end
---------------------------------------------------------------------------------------------------
Spice model from 1_shot.lib
---------------------------------------------------------------------------------------------------
*-------------------------------------------------------------------------
* CD4098B Retriggerable Monostable Multivibrator
*
* The CMOS Integrated Circuits Data Book, 1983, RCA Solid State
* rbh 06/14/91 Created
* rbh 06/04/92 Added dummy R/C pins
*
* Notes:
* 1. The RxCx and Cx pins are not functional. Instead, this model uses a
* simple PULSE width parameter to define the output pulse width tw(out).
* Note that this means that the pulse width is FIXED for the duration
* of the simulation. You can specify this value in the subcircuit call,
* e.g. X1 ... CD4098B PARAMS: PULSE=1.5ms
* 2. Trigger pulses which are shorter than the minimum input pulse width
* (70ns typ, 140ns max) produce an X at the outputs tw(out) in duration.
* When operating in non-retrigger mode (with QBar connected to TR-, etc.)
* this X output, because it is fed back into the inputs, will prevent
* the one-shot from clearing itself. This is correct (albeit pessimistic)
* behavior. This condition can be cleared by pulsing the RESET pin.
* 3. Because of its dependence on Rx and Cx values, minimum reset pulse
* width is not checked.
*
.subckt CD4098B RESET TR_POS TR_NEG Q QBAR
+ optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
+ params: PULSE=1us IO_LEVEL=0 MNTYMXDLY=0
*
*R1 CX 0 100MEG
*R2 CX 0 100MEG
*R3 RXCX 0 100MEG
*R4 RXCX 0 100MEG
*
UA inv VDD VSS
+ TR_NEG TR_NEGBAR
+ D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}
UTrigger or(2) VDD VSS
+ TR_NEGBAR TR_POS Trigger
+ D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}
UTrigBar inv VDD VSS
+ Trigger Trig_Bar
+ D0_GATE IO_4000B
*
UStart stim(1,1) VDD VSS
+ Clear
+ IO_STM
+ 0ns 0
+ 1ns Z
*
UClear and(2) VDD VSS
+ RESET TrigClear Clear
+ D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}
*
* Outputs cleared by RESET signal or delayed trigger
*
UOutputs jkff(1) VDD VSS
+ $D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR
+ D_CD4098B_Outputs IO_4000B IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY}
*
UTrigdly dlyline VDD VSS
+ Trigger trigdly
+ D_CD4098B_trigdly IO_4000B MNTYMXDLY={MNTYMXDLY}
UTrigx isx(1) VDD VSS
+ trigdly trigx
+ D0_GATE IO_4000B
*
UTrigx_bar inv VDD VSS
+ trigx trigx_bar
+ D0_GATE IO_4000B
UTrigx_barbar inv VDD VSS
+ trigx_bar trigx_barbar
+ D_CD4098B_tedge IO_4000B MNTYMXDLY={MNTYMXDLY}
UTrigx_fall and(2) VDD VSS
+ trigx_barbar trigx_bar trigx_fall
+ D0_GATE IO_4000B
*
UReset0 nor(2) VDD VSS
+ trigdly trigx_fall reset0
+ D0_GATE IO_4000B
*
UTrig0 is0(1) VDD VSS
+ Trigger Trig_0
+ D0_GATE IO_4000B
UTrig0_Bar inv VDD VSS
+ Trig_0 Trig0_Bar
+ D_CD4098B_edge IO_4000B MNTYMXDLY={MNTYMXDLY}
UTrigPreset or(2) VDD VSS
+ Trig_0 Trig0_Bar TrigPreset
+ D0_GATE IO_4000B
*
UTrigClear jkff(1) VDD VSS
+ TrigPreset $d_hi reset0 $d_lo $d_hi TrigClear $d_nc
+ D_CD4098B_pulse IO_4000B MNTYMXDLY={MNTYMXDLY}
*
* Local timing model
*
.model D_CD4098B_pulse ueff(
+ tpclkqhlmn={pulse-1ns+10ns}
+ tpclkqhlty={pulse-1ns+25ns} ; 25=tp(trigger)-tp(reset)
+ tpclkqhlmx={pulse-1ns+50ns}
+ )
.ends CD4098B
*
.model D_CD4098B_Outputs ueff (
+ twclklty=70ns twclklmx=140ns
+ tpclkqlhty=250ns tpclkqlhmx=500ns
+ tpclkqhlty=250ns tpclkqhlmx=500ns
+ tppcqhlty=225ns tppcqhlmx=450ns
+ tppcqlhty=225ns tppcqlhmx=450ns
+ )
.model D_CD4098B_trigdly udly (
+ dlymn=1ns dlyty=1ns dlymx=1ns
+ )
.model D_CD4098B_edge ugate(
+ tplhmn=1ns tplhty=1ns tplhmx=1ns
+ )
.model D_CD4098B_tedge ugate(
+ tphlmn=1ns tphlty=1ns tphlmx=1ns
+ )
*$
