Help to use CD4098B

I make the following circuit:


but I cannot start the simulator , see error message:
No compatibility mode selected!
warning, can’t find model tr_neg
warning, can’t find model tr_negbar
warning, can’t find model trigger
warning, can’t find model clear
warning, can’t find model reset
warning, model type mismatch in line
uoutputs jkff(1) vdd vss d_cd4098b_outputs io_4000b io_level={io_level} mntymxdly={mntymxdly}
warning, can’t find model trigger
warning, can’t find model trigdly
warning, can’t find model trigx
warning, can’t find model trigx_bar
warning, can’t find model trigx_barbar
warning, can’t find model trigdly
warning, can’t find model trigger
warning, can’t find model trig_0
warning, can’t find model trig_0
warning, can’t find model trigpreset
warning, can’t find model net-r2-pad2
warning, can’t find model net-r7-pad2
warning, can’t find model r
Circuit: KiCad schematic
Too many parameters for subcircuit type “cd4098b” (instance: xxu1)
Error: there aren’t any circuits loaded.


Spice Netlist

.include "/Users/max/Txt/WiperLand/rev2.0/WiperLand2/1_shot.lib"
.include "/Users/max/Txt/WiperLand/rev2.0/WiperLand2/BD675A.LIB"
XU1 GND Net-_C3-Pad1_ Net-_C2-Pad1_ Net-_C4-Pad2_ Net-_C5-Pad2_ Net-_U1-Pad11_ NC_01 GND Net-_R9-Pad2_ Net-_C5-Pad1_ Net-_U1-Pad11_ GND Net-_C2-Pad1_ Net-_C6-Pad1_ GND VCC CD4098B
C4 Net-_C2-Pad1_ Net-_C4-Pad2_ 100n
R4 Net-_C4-Pad2_ GND 10K
R6 Net-_C2-Pad1_ GND 100K
C2 Net-_C2-Pad1_ GND 100n
R2 VCC Net-_R2-Pad2_ Net-_R2-Pad2_ 1M
R3 Net-_R2-Pad2_ Net-_C3-Pad1_ 100K
C3 Net-_C3-Pad1_ GND 10u
R5 VCC Net-_C5-Pad2_ 100K
C5 Net-_C5-Pad1_ Net-_C5-Pad2_ 100n
R8 Net-_R7-Pad2_ Net-_C6-Pad1_ 100K
C6 Net-_C6-Pad1_ GND 10m
R7 VCC Net-_R7-Pad2_ Net-_R7-Pad2_ 1M
R9 Net-_Q1-Pad1_ Net-_R9-Pad2_ 4.7K
XQ1 Net-_Q1-Pad1_ /Vout GND bd675a
V1 VCC GND DC 12
R10 VCC /Vout R
( changed @ with # otherwise I cannot post )
.save #c4[i]
.save #r4[i]
.save #r6[i]
.save #c2[i]
.save #r2[i]
.save #r3[i]
.save #c3[i]
.save #r5[i]
.save #c5[i]
.save #r8[i]
.save #c6[i]
.save #r7[i]
.save #r9[i]
.save #v1[i]
.save #r10[i]
.save V(/Vout)
.save V(Net-_C2-Pad1_)
.save V(Net-_C3-Pad1_)
.save V(Net-_C4-Pad2_)
.save V(Net-_C5-Pad1_)
.save V(Net-_C5-Pad2_)
.save V(Net-_C6-Pad1_)
.save V(Net-_Q1-Pad1_)
.save V(Net-_R2-Pad2_)
.save V(Net-_R7-Pad2_)
.save V(Net-_R9-Pad2_)
.save V(Net-_U1-Pad11_)
.save V(Net-_U1-Pad7_)
.save V(VCC)
.tran 10m  10 0    10m uic 
.end
---------------------------------------------------------------------------------------------------
Spice model from 1_shot.lib
---------------------------------------------------------------------------------------------------

*-------------------------------------------------------------------------
* CD4098B  Retriggerable Monostable Multivibrator
*
* The CMOS Integrated Circuits Data Book, 1983, RCA Solid State
* rbh 06/14/91 Created
* rbh 06/04/92 Added dummy R/C pins
*
* Notes:
* 1. The RxCx and Cx pins are not functional.  Instead, this model uses a 
*    simple PULSE width parameter to define the output pulse width tw(out).
*    Note that this means that the pulse width is FIXED for the duration
*    of the simulation.  You can specify this value in the subcircuit call,
*    e.g. X1 ... CD4098B PARAMS: PULSE=1.5ms
* 2. Trigger pulses which are shorter than the minimum input pulse width
*    (70ns typ, 140ns max) produce an X at the outputs tw(out) in duration.
*    When operating in non-retrigger mode (with QBar connected to TR-, etc.)
*    this X output, because it is fed back into the inputs, will prevent 
*    the one-shot from clearing itself.  This is correct (albeit pessimistic)
*    behavior.  This condition can be cleared by pulsing the RESET pin.
* 3. Because of its dependence on Rx and Cx values, minimum reset pulse
*    width is not checked.
*
.subckt CD4098B RESET TR_POS TR_NEG Q QBAR
+	optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
+	params: PULSE=1us IO_LEVEL=0 MNTYMXDLY=0
*
*R1 CX 0 100MEG
*R2 CX 0 100MEG
*R3 RXCX 0 100MEG
*R4 RXCX 0 100MEG
*
UA inv VDD VSS
+ 	TR_NEG TR_NEGBAR
+	D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}
UTrigger or(2) VDD VSS
+	TR_NEGBAR TR_POS  Trigger
+	D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}
UTrigBar inv VDD VSS
+	Trigger Trig_Bar
+	D0_GATE IO_4000B
*
UStart stim(1,1) VDD VSS 
+	Clear
+	IO_STM
+	0ns	0
+	1ns	Z
*
UClear and(2) VDD VSS
+	RESET TrigClear Clear
+	D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}
*
* Outputs cleared by RESET signal or delayed trigger
*
UOutputs jkff(1) VDD VSS
+	$D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR
+	D_CD4098B_Outputs  IO_4000B IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY}
*
UTrigdly dlyline VDD VSS
+	Trigger trigdly
+	D_CD4098B_trigdly IO_4000B MNTYMXDLY={MNTYMXDLY}
UTrigx isx(1) VDD VSS
+	trigdly trigx
+	D0_GATE IO_4000B
*
UTrigx_bar inv VDD VSS
+	trigx trigx_bar
+	D0_GATE IO_4000B
UTrigx_barbar inv VDD VSS
+	trigx_bar trigx_barbar
+	D_CD4098B_tedge IO_4000B MNTYMXDLY={MNTYMXDLY}
UTrigx_fall and(2) VDD VSS
+	trigx_barbar trigx_bar trigx_fall
+	D0_GATE IO_4000B
*
UReset0 nor(2) VDD VSS
+	trigdly trigx_fall reset0
+	D0_GATE IO_4000B
*
UTrig0 is0(1) VDD VSS
+	Trigger Trig_0
+	D0_GATE IO_4000B
UTrig0_Bar inv VDD VSS
+	Trig_0 Trig0_Bar
+	D_CD4098B_edge IO_4000B MNTYMXDLY={MNTYMXDLY}
UTrigPreset or(2) VDD VSS
+	Trig_0 Trig0_Bar TrigPreset
+	D0_GATE IO_4000B
*
UTrigClear jkff(1)  VDD VSS
+	TrigPreset $d_hi reset0 $d_lo $d_hi TrigClear $d_nc
+	D_CD4098B_pulse IO_4000B MNTYMXDLY={MNTYMXDLY}
*
* Local timing model
*
.model D_CD4098B_pulse ueff(
+	tpclkqhlmn={pulse-1ns+10ns}
+	tpclkqhlty={pulse-1ns+25ns}	; 25=tp(trigger)-tp(reset)
+	tpclkqhlmx={pulse-1ns+50ns}
+	)
.ends CD4098B
*
.model D_CD4098B_Outputs ueff (
+	twclklty=70ns	  twclklmx=140ns
+	tpclkqlhty=250ns tpclkqlhmx=500ns
+	tpclkqhlty=250ns tpclkqhlmx=500ns
+	tppcqhlty=225ns  tppcqhlmx=450ns
+	tppcqlhty=225ns  tppcqlhmx=450ns
+	)
.model D_CD4098B_trigdly udly (
+	dlymn=1ns	dlyty=1ns	dlymx=1ns
+	)
.model D_CD4098B_edge ugate(
+	tplhmn=1ns	tplhty=1ns	tplhmx=1ns
+	)
.model D_CD4098B_tedge ugate(
+	tphlmn=1ns	tphlty=1ns	tphlmx=1ns
+	)
*$

Please edit your posting.

If you look at it in the browser, the text is barely readable. You may use the button “Preformatted Text”, or place three tildes in series each in front of and behind your netlists and model descriptions.

EDIT: Thanks for updating your post.

The model for the CD4098B is using U devices like

UClear and(2) VDD VSS

These U devices are unfortunately not supported by ngspice, so this circuit cannot be simulated.

What is a dual monostable supported by ngspice ?

I have found a CD14538B library, I make a new wiring diagram, but cannot run.
Sorry I am new to use simulation.

Error message:

warning, can't find model r
warning, can't find model vcc
Circuit: KiCad schematic
Error on line 9 :
u1 0 net-_c3-pad1_ vcc vcc net-_r5-pad2_ net-_r9-pad2_ nc_01 0 vcc cd14538b
Unable to find definition of model vcc
Error: circuit not parsed.

Netlist Spice:

.include "/Users/max/Txt/WiperLand/library_spice/BD675A.LIB"
R3 VCC Net-_C3-Pad1_ 1M
C3 Net-_C3-Pad1_ GND 10u
R5 VCC Net-_R5-Pad2_ 100K
R9 Net-_Q1-Pad1_ Net-_R9-Pad2_ 4.7K
XQ1 Net-_Q1-Pad1_ /Vout GND bd675a
R10 VCC /Vout R
U1 GND Net-_C3-Pad1_ VCC VCC Net-_R5-Pad2_ Net-_R9-Pad2_ NC_01 GND VCC CD14538B
V1 VCC GND DC 12
.save @r3[i]
.save @c3[i]
.save @r5[i]
.save @r9[i]
.save @r10[i]
.save @v1[i]
.save V(/Vout)
.save V(Net-_C3-Pad1_)
.save V(Net-_Q1-Pad1_)
.save V(Net-_R5-Pad2_)
.save V(Net-_R9-Pad2_)
.save V(Net-_U1-Pad7_)
.save V(VCC)
.tran 10m  10 0    10m uic 
.end

CD14538B model:

* Developed: ETech (eetech00@yahoo.com)
* Created: Dec 04 2017
* Revision: Aug 03 2020
*
* This CD14538B spice behavioral model was tested
* with LTSpice. Temperature is not modeled.
*
* Texas Instruments
* CD14538B CMOS Dual Precision Monostable Multivibrator
*
* block symbol definitions
.subckt CD14538B +TR -TR _RST CX CRX Q _Q VDD VGND
A6 0 Q1 0 QS 0 QR 0 0 OR tau={tau} tripdt={tdt}
A7 0 CMP2 POR+R QR 0 QS 0 0 OR tau={tau} tripdt={tdt}
XX1 D _CL CL _POR+R CMP1 Q1 _Q1 ff params: Tau={tau} Tdt={tdt} Td=1n
A4 QR 0 0 0 0 _QR 0 0 BUF tau={tau} tripdt={tdt}
A10 _QR1 0 0 0 0 QR2 0 0 BUF tau={tau} tripdt={tdt}
A11 QR1 0 0 0 0 _QR1 0 0 BUF tau={tau} tripdt={tdt}
A13 0 _+TR 0 -TR-1 0 CLK 0 0 AND tau={tau} tripdt={tdt}
A15 0 POR 0 R 0 _POR+R 0 0 OR tau={tau} tripdt={tdt}
A17 _QR 0 0 0 0 QR1 0 0 BUF tau={tau} tripdt={tdt}
A1 CMP RLO 0 0 0 0 C1 0 SCHMITT vt=0.0 vh=100u tau={tau} tripdt={tdt}
A3 _Q1 0 0 0 0 Q2 0 0 BUF tau={tau} tripdt={tdt}
V1 1 0 1
A5 CMP RHI 0 0 0 0 C2 0 SCHMITT vt=0.0 vh=100u tau={tau} tripdt={tdt}
A19 _POR+R 0 0 0 0 POR+R 0 0 BUF tau={tau} tripdt={tdt}
S2 C2A CMP2 _QR 0 SW
XX2 QR2 _QR2 QR1 inv2 params: tau={tau} tripdt={tdt} Tau={tau} Tdt={tdt} vhigh={lh}
V3 Qout _QR 0
V4 _Qout QR 0
R1 RHI CX1 754.5k
R2 VDD2 RHI 245.5k
S3 VGND CX1 3P 3N CSW
AE1 _QR 0 0 0 0 3N 3P 0 BUF tau={tau} tripdt={tdt}
R3 RLO VGND 333.3k
R4 P001 RLO 666.6k
S4 P001 VDD2 4P 4N CSW
AE2 _Q1 0 0 0 0 4P 4N 0 BUF tau={tau} tripdt={tdt}
R6 CMP CRX 100
S7 VGND PO 7P 7N SW4
AE5 CTL 0 0 0 0 7N 7P 0 BUF tau={tau} tripdt={tdt}
B2 CTL 0 V=(V(VDD,VGND)>0.5*V(VDD)?1:0)
C2 VDD2 PO 100p
XX5 Qout _Q VGND VDD2 cd40_out_10a params: Tau={tau} Tdt={tdt} Td={tdo} Lh={lh}
XX6 _Qout Q VGND VDD2 cd40_out_10a params: Tau={tau} Tdt={tdt} Td={tdo} Lh={lh}
XX7 _RST R VDD2 VGND cd40_in_11 params: Tau={tau} Tdt={tdt} Td={td} Lh={lh}
B3 VD2 VGND V=V(VDD,VGND)
R9 VDD VGND R=Limit(200k,QRes(),1e6)
E1 VDD2 VGND VD2 VGND 1
C5 10 VGND 10p
R10 VD2 10 100
B1 POR 0 V=(V(PO)>0.5*V(VDD,VGND)?1:0)
S8 D 1 8P 8N SW
AE6 CL 0 0 0 0 8P 8N 0 BUF tau={tau} tripdt={tdt}
R12 CMP2 0 100k
XX8 CLK _CL CL cd40_clk_1 params: Tau={tau} Tdt={tdt} Td=1n
D1 CRX VDD2 DIO1
D2 VGND CRX DIO1
V5 CX VGND 0
A8 _-TR 0 0 0 0 -TR-1 0 0 BUF tau={tau} tripdt={tdt}
XX11 C2 _QR2 C2A QR1 cd40_tg_10 params: tau={tau} tdt={tdt} td={td}
XX12 C1 _Q1 CMP1 Q1 cd40_tg_10 params: tau={tau} tdt={tdt} td={td}
R7 D 0 1Meg
XX3 +TR _+TR VDD2 VGND cd40_in_s_2 params: Tau={tau} Tdt={tdt} Td={td} Lh={lh}
XX4 -TR _-TR VDD2 VGND cd40_in_s_2 params: Tau={tau} Tdt={tdt} Td={td} Lh={lh}
M2 NDPD NG VGND VGND NMOS1
M1 NDPD PG VDD2 VDD2 PMOS1
R8 PG1 PG 100
R11 NG1 NG 100
B4 NG1 VGND V=V(VDD2)*V(Q2,0)
R13 Q2 0 1Meg
B5 PG1 VDD2 V=V(VDD2)*V(_QR,0)
R14 _QR 0 1Meg
R15 PG VDD2 50k
R16 VGND NG 50k
R5 CRX NDPD 100
.model SW SW(Ron={Ron} Roff={Roff} Vt=0.5 Vh=-0.4)
.param tau = 10n
.param tdt = 1n
.param td = 2n
.param lh = 1
.param tdo = 150n
.model SW4 SW(RON=1e4 ROFF=1G VT=0.5 VH=-0.1)
.ic V(Q1)=0 V(_Q1)=1
.param Ron=1 Roff=10Meg
.func QRes () {V(VDD)/If(V(VDD)<=5,5uA,If(V(VDD)<=10,10uA,if(V(VDD)<=15,20uA,100uA)))}
.model CSW SW(Ron={Ron} Roff={Roff} Vt=0.5 Vh=-0.4)
.MODEL NMOS1 NMOS ( LEVEL=3  W=500e-6  L=4E-6  VTO=1
+ VMAX=1E6  RS=10  RD=10  CJ=0.002  MJ=0.4
+THETA=1E-6 ETA=0.01  KAPPA=2.2)
.MODEL PMOS1 PMOS ( LEVEL=3  W=500e-6  L=4E-6  VTO=-1
+ VMAX=1E6  RS=10  RD=10  CJ=0.002  MJ=0.4
+THETA=1E-6 ETA=0.01  KAPPA=2.2)
.MODEL DIO1 D (IS=10p RS=10 N=1.75 M=0.4 Cjo=6p TT=20n)
.ends CD14538B

.subckt ff D _CL CL _R1 _R2 Q _Q
XX1 Di CL Dio _CL cd40_tg_10 params: tau={tau} tdt={tdt} td={td}
XX2 Dio _CL _Q CL cd40_tg_10 params: tau={tau} tdt={tdt} td={td}
XX4 D CL Dn _CL cd40_tg_10 params: tau={tau} tdt={tdt} td={td}
A1 Di 0 0 0 0 Dn 0 0 BUF tau={tau} tripdt={tdt}
A2 Dio 0 0 0 0 Q 0 0 BUF tau={tau} tripdt={tdt}
A7 0 _R1 _R2 D 0 Di 0 0 AND tau={tau} tripdt={tdt}
A3 0 Q _R2 _R1 0 _Q 0 0 AND tau={tau} tripdt={tdt}
.param tau=50n
.param tdt=10n
.param td=2n
.param lh=1
.ic V(_CL)=1 V(CL)=0
.ends ff

.subckt inv2 A _A Ena
A1 A 0 0 0 0 _A 0 0 BUF tau={tau} tripdt={tdt}
S1 _A 0 ENA 0 SW
.model SW SW(VT={lh*0.5} VH=-0.1 Ron=10 Roff=1G)
.param tau=50n
.param tdt=10n
.param td=2n
.param lh=1
.ends inv2

.subckt cd40_out_10a IN OUT VGND VDD
S1 VDD out20 _CTL CTL SW1 OFF
S2 out20 VGND CTL _CTL SW2 OFF
R1 OUT out20 {Rout}
A1 IN 0 0 0 0 _CTL CTL 0 BUF tau={tau} tripdt={tdt} td={td}
.param Rout=1m
.param Ron1=384.6 Ilim1=6.8m
.param Ron2=384.6 Ilim2=6.8m
.model SW1 SW Ron={Ron1} Vt=.5 Vh=-0.3 Ilimit={Ilim1}
.model SW2 SW Ron={Ron2} Vt=.5 Vh=-0.3 Ilimit={Ilim2}
.IC V(CTL)=0
.param tau = 50n
.param tdt = 10n
.param td = 1n
.ends cd40_out_10a

.subckt cd40_in_11 in _out VDD VGND
R1 in out10 10k
C1 out10 VGND 1.8p
R2 in VGND 1e8
B1 out20 0 V=LIMIT(0,V(out10,VGND)*1/V(VDD),1)
AE1 out20 0 0 0 0 _out 0 0 BUF tau={tau} tripdt={tdt}
R3 VGND VDD 1e8
.param tau = 50n
.param tdt = 10n
.ends cd40_in_11

.subckt cd40_clk_1 IN _CL CL
A7 IN 0 0 0 0 _IN 0 0 BUF tau={tau} tripdt={tdt} td={td} Vhigh={lh}
A8 IN 0 0 0 0 0 IN-1 0 BUF tau={tau} tripdt={tdt} td={td}
A11 0 _IN 0 td1 0 td2 0 0 AND tau={tau} tripdt={tdt}
A1 0 IN-1 0 td2 0 td1 0 0 AND tau={tau} tripdt={tdt}
A2 td3 0 0 0 0 _CL 0 0 BUF tau={tau} tripdt={tdt} td={td} Vhigh={lh}
A9 td4 0 0 0 0 CL 0 0 BUF tau={tau} tripdt={tdt} td={td} Vhigh={lh}
A3 td1 0 0 0 0 td3 0 0 BUF tau={tau} tripdt={tdt} td={td} Vhigh={lh}
A4 td2 0 0 0 0 td4 0 0 BUF tau={tau} tripdt={tdt} td={td} Vhigh={lh}
.param tau=50n
.param tdt=10n
.param td=1n
.param lh=1
.ends cd40_clk_1

.subckt cd40_tg_10 IN N OUT P
S1 OUT IN Nn 0 SW OFF
S2 OUT IN Pi 0 SW OFF
A1 N 0 0 0 0 0 Nn 0 BUF tau={tau} tripdt={tdt}
A2 P 0 0 0 0 Pi 0 0 BUF tau={tau} tripdt={tdt}
.model SW SW(Ron=10 Roff=1G Vt=.5 Vh=-0.1)
.param tau=50n tdt=10n td=2n
.ends cd40_tg_10

.subckt cd40_in_s_2 in _out VDD VGND
R1 in out10 10k
C1 out10 VGND 1.8p
R2 in VGND R=Limit(3e6,18e6,V(in)/0.1uA)
B1 out20 0 V=LIMIT(0,V(out10,VGND)*(1/V(VDD)),1)
R3 VGND VDD 1e8
A1 out20 0 0 0 0 _out 0 0 SCHMITT tau={tau} tripdt={tdt} vt={vt1} vh={vh1}
.param tau=50n
.param tdt=10n
.param vt1=2.5/5
.param vh1=1.0/5
.ends cd40_in_s_2

The model seems not to be instanciated correctly. If you have the symbol, you have to attach its spice model as a subcircuit model to its symbol.

Unfortunately this model again will not run with ngspice. Whereas the former used internally U devices which are specific to PSPICE (and perhaps microCap), the latter model uses A devices like

A6 0 Q1 0 QS 0 QR 0 0 OR tau={tau} tripdt={tdt}

which are specific to LTSPICE only.

Ok, thanks for your support.

We never give up!

Attached you will find a model of a 5V CD4538 (https://www.ti.com/lit/gpn/cd54hc4538) which will run with ngspice. It stems from https://forums.ni.com/ni/attachments/ni/370/4261/1/CD4538BCN.txt : I have modified it slightly to make reset work. I have added a netlist file running with standard ngspice showing normal output pulses as well as re-triggered and reset pulses.

CD4538BCN.lib (1.6 KB) Test-CD4538.cir (847 Bytes)

4 Likes

Hi Holger,
great !!!
but can I use with Kicad ?
See error message:

No compatibility mode selected!
warning, can't find model r
Circuit: KiCad schematic
Reducing trtol to 1 for xspice 'A' devices
Doing analysis at TEMP = 27,000000 and TNOM = 27,000000
Fatal error: instance v.xu1.v2 is a shorted VSRC
doAnalyses: operation not supported
run simulation(s) aborted

Spice netlist:

title KiCad schematic
.include "/Users/max/Txt/WiperLand/library_spice/BD675A.LIB"
.include "/Users/max/Txt/WiperLand/Simulatore/CD4538BCN.lib"
R3 VCC Net-_C3-Pad1_ 1M
C3 Net-_C3-Pad1_ GND 10u
R5 VCC Net-_R5-Pad2_ 100K
R9 Net-_Q1-Pad1_ Net-_R9-Pad2_ 4.7K
XQ1 Net-_Q1-Pad1_ /Vout GND bd675a
R10 VCC /Vout R
XU1 GND Net-_C3-Pad1_ VCC VCC Net-_R5-Pad2_ Net-_R9-Pad2_ NC_01 GND VCC 4538
V1 VCC GND DC 5
.save @r3[i]
.save @c3[i]
.save @r5[i]
.save @r9[i]
.save @r10[i]
.save @v1[i]
.save V(/Vout)
.save V(Net-_C3-Pad1_)
.save V(Net-_Q1-Pad1_)
.save V(Net-_R5-Pad2_)
.save V(Net-_R9-Pad2_)
.save V(Net-_U1-Pad7_)
.save V(VCC)
.tran 10m  10 0    10m uic 
.end

Yes, of course:

R10 VCC /Vout R

What is that? Give a value instead of R

Put C3 between CX and CRX, as prescribed by the data sheet. Do not set pin CX to GND (it is grounded internally, which conflicts with external ground).

Make wiring diagram corrections:


See error message:

No compatibility mode selected!
Circuit: KiCad schematic
Reducing trtol to 1 for xspice 'A' devices
Doing analysis at TEMP = 27,000000 and TNOM = 27,000000
Fatal error: instance v.xu1.v2 is a shorted VSRC
doAnalyses: operation not supported
run simulation(s) aborted

Spice netlist:

.title KiCad schematic
.include "/Users/max/Txt/WiperLand/library_spice/BD675A.LIB"
.include "/Users/max/Txt/WiperLand/Simulatore/CD4538BCN.lib"
R3 VCC Net-_C3-Pad1_ 1M
C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10u
R5 VCC Net-_R5-Pad2_ 100K
R9 Net-_Q1-Pad1_ Net-_R9-Pad2_ 4.7K
XQ1 Net-_Q1-Pad1_ /Vout GND bd675a
R10 VCC /Vout 1k
XU1 Net-_C3-Pad2_ Net-_C3-Pad1_ VCC VCC Net-_R5-Pad2_ Net-_R9-Pad2_ NC_01 GND VCC 4538
V1 VCC GND DC 5
.save @r3[i]
.save @c3[i]
.save @r5[i]
.save @r9[i]
.save @r10[i]
.save @v1[i]
.save V(/Vout)
.save V(Net-_C3-Pad1_)
.save V(Net-_C3-Pad2_)
.save V(Net-_Q1-Pad1_)
.save V(Net-_R5-Pad2_)
.save V(Net-_R9-Pad2_)
.save V(Net-_U1-Pad7_)
.save V(VCC)
.tran 10m  10 0    10m uic 
.end

Of the four steps to be done for enabling the simulation

select a symbol
select a model
attach the model to the symbol
match the symbol’s node sequence to that of the model

the last step seems to be missing in your circuit setup.

For a general introduction please see http://ngspice.sourceforge.net/ngspice-eeschema.html#OpAmp

In your special case you have a symbol with nodes

1   2   3   4   5  6  7    8   16
CX CRX RST +TR -TR Q Qnot GND VDD

This is the node sequence which up to now has been sent from Eeschema to ngspice

The model from CD4538BCN.lib has the following sequence, derived from its .subckt line by copying the third and onward tokens (the first would have been .subckt, the second 4538 is the subcircuit name). Then the nodes are following:

CD A B T1 T2 Q NOTQ VDD VSS

This is what ngspice is expecting to get from Eeschema, because it will use it to instantiate the subcircuit.

Firstly we have to translate it by node names (by inspection of the model file, the most difficult step here …)

CD  A   B   T1  T2 Q NOTQ VDD VSS
CX CRX RST +TR -TR Q Qnot VDD GND

This will result in
RST +TR -TR CX CRX Q NOTQ VDD VSS
usng your symbol’s node names

Then we have to have a look at the equivalent (translated) node number sequence
3 4 5 1 2 6 7 16 8

Eeschema now has a means to take this change in node number sequence into account, the ‘Alternate node sequence’. You will have to enter the new node number sequence from above into the text field and tick the associated box. Then Eeschema will send the new node sequence to ngspice, and everything should be o.k.

Note: I did not test this new sequence, I do not have an Eeschema circuit sketch available.

B.t.w.: The dark scheme of your circuit diagram is more difficult to read (for me) than any light scheme.

1 Like

One now might ask: Why is this so complex in Eeschema/ngspice? When I use another xSPICE simulator, I don’t need to care about node sequences.

Indeed, in Eeschema the node numbers of a symbol have a meaning: Each node number is the corresponding pin number of my device footprint. This is an important link between circuit and PCB layout. Pure spice simulators don’t care about layout, symbol node numbers are simply chosen to match the model’s connection numbers. And unfortunately all the model makers serve foremost the xSPICE simulators.

This is especially of interest when looking at the image attached to the first post of this tread.

(A change in circuit design is needed: pins 1 and 15 are not pins to be grounded, but are Cx1 and Cx2, taking the other end of the respective capacitor.)

There we have three units U1, U2, U3 of the device 4538 (or 4098), and we have 16 pins, numbered according to the 16-pin package of the IC. How to handle that?

One has to attach a model to each of the units. There are now 2 ways to do this:

Attach the existing model from file CD4538BCN.lib to each unit, set the alternate node sequence, but when at unit U1B replace the former nodes 1 to 7 by the equivalent nodes 9 to 15.

Another way might be to create a top level subcircuit which takes into account the node sequence and includes two instances of the model. This subcircuit then again has to be attached to all three units of the IC, but the node sequence is cared for automatically.

The pin number and pin name sequence (from the data sheet):

 1   2      3      4    5   6  7   8   9  10  11   12    13    14    15  16
CX1 RXCX1 RESET1 +TR1 -TR1 Q1 _Q1 VSS _Q2 Q2 -TR2 +TR2 RESET2 RXCX2 CX2 VDD

So lets define the subcircuit (token .subckt, followed by subcircuit name and the nodes, close subcircuit by .ends):

.subckt 4538TOP CX1 RXCX1 RESET1 +TR1 -TR1 Q1 _Q1 VSS _Q2 Q2 -TR2 +TR2 RESET2 RXCX2 CX2 VDD
.ends

Add the model file to be included:

.subckt 4538TOP CX1 RXCX1 RESET1 +TR1 -TR1 Q1 _Q1 VSS _Q2 Q2 -TR2 +TR2 RESET2 RXCX2 CX2 VDD
.include CD4538BCN.lib
.ends

Add the two device instances

.subckt 4538TOP CX1 RXCX1 RESET1 +TR1 -TR1 Q1 _Q1 VSS _Q2 Q2 -TR2 +TR2 RESET2 RXCX2 CX2 VDD
.include CD4538BCN.lib
XU1A CD A B T1 T2 Q NOTQ VDD VSS 4538
XU1B CD A B T1 T2 Q NOTQ VDD VSS 4538
.ends

Now set the correct connections between top level nodes and instance nodes:

.subckt 4538TOP CX1 RXCX1 RESET1 +TR1 -TR1 Q1 _Q1 VSS _Q2 Q2 -TR2 +TR2 RESET2 RXCX2 CX2 VDD
.include CD4538BCN.lib
XU1A RESET1 +TR1 -TR1 CX1 RXCX1 Q1 _Q1 VDD VSS 4538
XU1B RESET2 +TR2 -TR2 CX2 RXCX2 Q2 _Q2 VDD VSS 4538
.ends

Put this into a file (e.g. 4358top.lib) and attach this model (not the original one!) to all three units.

Note again: not tested

1 Like

I follow your indications, but one more problem:


see error message:

No compatibility mode selected!
Circuit: KiCad schematic
Reducing trtol to 1 for xspice 'A' devices
Doing analysis at TEMP = 27,000000 and TNOM = 27,000000
Using transient initial conditions
**** ERROR ****
* CLIMIT function linear range less than zero. *
 Reference value :  1,00000e-04

No. of Data Rows : 3131

Spice netlist

.title KiCad schematic
.include "/Users/max/Txt/WiperLand/library_spice/BD675A.LIB"
.include "/Users/max/Txt/WiperLand/Simulatore/CD4538BCN.lib"
R3 VCC Net-_C3-Pad1_ 1M
C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10u
R9 Net-_Q1-Pad1_ Net-_R9-Pad2_ 4.7K
XQ1 Net-_Q1-Pad1_ /Vout GND bd675a
R10 VCC /Vout 1k
XU1 VCC VCC Net-_R1-Pad1_ Net-_C3-Pad2_ Net-_C3-Pad1_ Net-_R9-Pad2_ NC_01 VCC GND 4538
V1 VCC GND dc 5
V2 Net-_R1-Pad2_ GND dc 5 pulse(5 0 .1 1u 1u .1 .2)
R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 680
R2 Net-_R1-Pad1_ GND 68
.save @r3[i]
.save @c3[i]
.save @r9[i]
.save @r10[i]
.save @v1[i]
.save @v2[i]
.save @r1[i]
.save @r2[i]
.save V(/Vout)
.save V(Net-_C3-Pad1_)
.save V(Net-_C3-Pad2_)
.save V(Net-_Q1-Pad1_)
.save V(Net-_R1-Pad1_)
.save V(Net-_R1-Pad2_)
.save V(Net-_R9-Pad2_)
.save V(Net-_U1-Pad7_)
.save V(VCC)
.tran 10m  10 0    10m uic 
.end

This seems to be a reaction of the model to uncommon (or wrong?) input.

Please read the data sheet.

“An unused “A” input should be tied to GND” (A == +TR)

What is the input to -TR meant to be?

Please have a look at my example circuit how to excite the circuit.

1 Like

Hello @atomino

The 4098 and the 4538 are MONOSTABLE devices. They need a pulse on either +TR or -TR to operate and the other TR must be tied to either Vcc or Gnd (See data sheet for explanation). You have some mid-range voltage on -TR which will just cause the IC to emit “magic smoke” in time. There is no input pulse source.
Also, your timing resistor and capacitor choices are really pushing the boundaries of the IC.
Output current of this device, I don’t think, is high enough to use directly to operate the darlington, and finally, these monostables have a propagation delay between trigger and output, so, if you want an immediate response from a trigger, this is not a component to choose.

Sorry, but the simulator just won’t work with your existing circuit.