Also check that the zone is assigned the “GND” net.
Thank you for your quick replies. Although I changed settings I didn’t solve the problem. One more photo is below. You can see that it connects to other GND pins except those on the ATMEGA328. 
It definitely looks like a clearance / min width issue. Try changing these settings in the Zone Properties. Or post a screen shot of your Zone Properties dialog.
The first figure shows my initial (default) settings. The second is the one I changed. I tried other values as well, but I must admit that I have not experience of this.
The default settings should have been okay. Are you sure you are pressing the ‘B’ key to refill all zones? I don’t know if the shortcut keys change for different languages. You can press the ‘?’ key and look for “Fill or Refill all zones”, it’s at the bottom of my list.
Or something like: “Ispunite ili ponovno napunite sve zone”
Yes, the B key works. I also right click and choose fill or refill all zone, its the same.
And it is still not working.
Perhaps it is the clearance of the pads themselves. Do you get any DRC errors besides the unconnected nets?
No, it shows no problems/markers, just unconnected ones…
At one moment the fill appeared inside the chip ATMEGA328 but it was still not connected to the GND pins of the chip from the outside, just from the inside. STRANGE. Now I can’t get back in that state to make a photo…
Can you place the cursor over U2, but not over any pad or track, and press ‘E’ and post a pic of that dialog?
Anyone else got any ideas?
Often I find the zone fill doesn’t quite get everywhere, I usually work around it by connecting a trace between pads. It has to be pad to pad, not pad to zone, i.e. you can’t leave a trace dangling into a zone and have it connect (I think that works in Eagle).
Looks like your Default (and any other net classes containing pins around your GND pins) net class has too high of a clearance setting.
EDIT: And move Y1’s reference off of C5, you’re upsetting your oscillator.
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@1.21Gigawatts here is a photo of U2 properties (pressed E)
bobc I guess I will do the same if I don’t solve it any other way. Thanks!
@jwpartain1 I don’t understand why the C5 has to be removed. Isn’t that a standart technique to connect a crystal to two capacitors and than capacitors to ground?
Thank you all for your effort.
I have done it as @bobc suggested - connecting GND pad from U2 chip to another gnd pad. The space inside the chip became filled up with ground. I guess we solved the problem, I don’t know if it is a good way but I suppose it works. Any comments on this are very welcome
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Your circuit architecture is correct. DO NOT remove the physical component C5. The problem is the silk-screen reference designator, “Y1”. It is located on top of pad2 of C5. The silk-screen ink on the bare copper will interfere with soldering C5 to the board.
(The DRC in KiCAD does not look for silkscreen violations. The board designer must do this on his own before sending Gerbers to a board fabricator. Some fabricators will find an error like this and remove the silk-screen from the bare copper - perhaps leaving behind an illegible spattering of silkscreen where the lettering was supposed to be. Other fabricators will build the board as designed, and let the designer figure out how to salvage the boards.)
Dale
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Your symptoms still sound like a conflict over required clearances, minimum trace widths, etc, between the fill zone and the pads on the ATMega part. As you say, the routing is now complete and very acceptable so there is no reason (other than your personal understanding of KiCAD’s behavior) to put more effort into solving the problem.
I always place traces - usually very thin traces - that connect all pads to their nets, even if the pads are inside a fill zone. This gives me confidence that the fill zone can actually make the connections to the pads. The fill zone should overlay the traces and nobody will ever know they are there.
Dale
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You do not want an upset oscillator! That could create upset engineers, upset supervisors, and upset customers.
Dale
A few things to improve.
Drag C1 down a little to reduce the 5V track length.
Add a 2nd decoupler near the “6” of 16MHz.
Try to put the crystal and it’s capacitors closer to the cpu
These will make your board quieter