GND fill connects, VCC does not

[paulvdh]

There does indeed seem to be no room for thermal reliefs.
Note that pad A49 in the first screenshot is also not connected to the GND plane.

Connecting pads with manual laid down tracks is quite common when the thermal via’s don’t work.

I’m not sure about your 3rd post (2nd screenshot) with the brown layer. Are you sure it’s set to the correct net?

Sometimes it helps to rotate the pad 45 degrees in the footprint editor. Or, the pads in your connector footprint are probably already roated to get the spokes to connect diagonally instead of horizontally and vertically.

I’m willing to have a look at your project. Can you post a simplified version here, with just the connector, some other parts to connect to so the nets are preserved and a (rectangular) PCB outline.

[Piotr]

@Alan

but I had to manually add traces to internal GND pins because the flow did not go into the inter pin area even though the settings are the same:

When I place fill area I always change its Clearance to 0.25, Minimu width to 0.2, Thermal relief gap to 0.25 and Thermal spoke width to 0.25.
I suppose GND fill with such settings (or even smaller) will have a chance to reach B40 pin.

[mf_ibfeew]

I will try to experiment with the zone priorities, but if these are on different layers, will priority even play a role? There shouldn’t be any conflicts there, I would think.

That was only a general remark, independent from the shown project/problem. Assigning unique priorities will prevent conficting zones (sooner or later).

I second pauls question about the project - only with an example project it’s useful to investigate further (complete project archive, not only board-file. Use the archive-command from the main kicad manager).

[Alan]

Thank you for the suggestions on the plane settings. Honestly, I wasn’t really sure what I should do there so I left it at the defaults. I’ve changed it and the copper now flows into the internal area on the ground plane. So that problem is resolve. Unfortunately, the VCC issue still remains. I’ve attached a screenshot of just VCC (GND is hidden) showing progression closer to the VCC pans, but they are still not connected.

I’ll try to build up a sample project that demonstrates the issue and send that along. It might take me a bit, however, as this isn’t a day job project.

[Alan]

I did decide to try the “solid” pad connection option, and I confirmed my memory from last night. As shown below, the VCC pads are now connected. Interestingly, however, the un-routed lines are still shown, however, so it seems like parts of the system are still confused.

[Alan]

Paul,
I’m sorry… I neglected to address some of your observations… A49 became connected, along with many of the internal pads, once I changed the relief data per the suggestions. At this point, the GND layer seems to be correct.

As for the third post. Yes, that is definitely the Vcc layer, and the crux of the problem. Even after fine tuning some of the configurations, the VCC layer still fails to address the unrouted pins (shown on the screen) even though they are the same net as the brown plane.

I’ve actually gotten the unrouted lines to go away if I manually route bridges between the pads and the plane (effectively performing a manual thermal relief). However, this still results in entries for those connections within the “Unconnected Items” tab of the ERC. maybe that isn’t important?

[Alan]

Cool… I was able to create a small sample project that has the TE connector and two diodes. The diodes are just there to show that the thermal relief and connections work on them completely (both ground and VCC), but the same behavior is not seen on the connector.

Now the problem… As a new user, I cannot upload attachments. . Is there a different KiCAD forum where I can elicit help without the restrictions? I get why they exist…I wish they did on phones! (I’ve had 3 spam phone calls today already…), but it is tough when you are both fighting KiCAD and spambots at the same time. sigh.

[paulvdh]

The anti spam bot is a bit annoying sometimes indeed. Especially when on a new forum and having put in effort to make such a test case.

Some moderators can bump users up a trust level, but I have not managed to do that.
You can read more about the automated mechanism below:

New Member Information

The Kicad Forum uses the Discourse program to operate. To understand this system, please read the information in this link: https://blog.discourse.org/2018/06/understanding-discourse-trust-levels/ As a new user (Level 0 - New), there are many restrictions, among which are: Only one image may be posted No attachments may be posted. To post multiple images and/or attachments, the new member needs to achieve (Level 1 - Basic). Level 1 is achieved by opening and reading at least Thirty differe…

I think you get bumped automatically if you scroll slowly (“reading”) just three more unrelated threads.

[hermit]

There was a ‘bump in the night’.

[Alan]

Thumpity, thump… (thank you)…

Here is a simple project file that demonstrates the behavior I’m seeing.
testroute.zip (123.3 KB)

One thing of interest while looking at this… If you tinker with the ‘solid’ option (versus thermal relief), it seems like KiCAD isn’t really abiding by the clearances. In fact, it almost seems as though the fill goes all the way to the hole, which would effectively short all the pads out. That would certainly not be good… Mind you, I might be misinterpreting the image coloring.

[paulvdh]

First, before I forget. It looks like both D1 and D2 are shorting your power supply…

@Alan

it almost seems as though the fill goes all the way to the hole, which would effectively short all the pads out. That would certainly not be good… Mind you, I might be misinterpreting the image coloring.

It does indeed seem so, but it’s not a fact.
You can see this in the 3D view [Alt + 3] and then disable the “board” and the mask layer. KiCad has the ability to remove the annular rings for THT pads on layers for which there is no connection, and when looking perpendicular at the PCB the gap in the inner layers is covered by the annular ring on the outer layers of the PCB. In the 3D viewer it looks like:

If you show the pads in outline mode with PCB Editor / View / Drawing Mode / Sketch Pads then it also becomes clearer. You can also use the button on the left toolbar:

There seems to be some kind of interference between the size of the pads and the distance between the pads. In the screenshot below, (with pads in outline mode) I have also modified all pads to make them a littlebit smaller. They were 1.524mm, and I shrunk them to 1.5mm All pads of both the GND net and the VCC net now connect as expected.

You can do this yourself with:

1. Select the footprint in the PCB editor, and press [Ctrl + E] to load it in the footprint editor.
2. Select a random pad (I used B1) press e for edit and change Pad Size X to 1.5mm.
3. Accept this change by clicking on [ OK ] to close the pad edit window.
4. Right click (anywhere on the PCB as long as that B1 pad is still selected).
5. In the popup menu, select Copy Pad Properties to Default
6. Select the other pads (there is a difference between swiping from left to right and from right to left).
7. Right click again but now select Paste default Pad Properties to Selected
8. Close the Footprint Editor. KiCad prompts you with a “Save before closing” window. Select [ Save ]
9. You’re now back in the PCB editor. You may have to press b to refill the zones.

2022-11-23_testroute.zip (102.6 KB)

With that change it looks a lot better but I’m not entirely sure why the small difference in the pad size matters.

---

In this next variant I did not change the pad size, but instead changed the pad properties to: Copper layers: F.Cu, B.Cu and connected layers in the footprint editor for all the pads (except mounting holes). With this setting Kicad can also create the thermal spokes for all the pads.

2022-11-23T02:49_testroute.zip (99.8 KB)

I’m not exactly sure where the limits are, but a thumbs up to mf_ibfeew for noticing:

@mf_ibfeew

The thermal spokes-algorithm seems to have difficulties with many pads on an o small area

Now it’s time to close my eyes for a few hours and hopefully be a bit clearer when I open them again.

[Alan]

Paul… First and foremost, a hearty thank you for the greatly appreciated effort you have put forth… I’m just getting back from different evening obligations, but I will read through this more carefully tomorrow and try the suggestions.

I kind of assumed that the clearance would be better on middle layers, but I wasn’t sure how to concretely confirm that. The 3D viewer is an interesting tool that I had not played with. I shall have to add that to my repertoire of ideas… cool

As for the shorting with the diodes. LOL. I was wondering if anyone would notice that! hehehe. Of course, it was just a simple and meaningless sample. The diodes were effective because they were thru hole components that I could easily bind to VCC and GND. The diodes were, believe it or not, kind of an intentional pun that I’m tickled you saw.

Again, thank you to to everyone that has put forth ideas and help. It is always great when others are willing to take the time to help throw a life ring to others. I do this quite frequently in other forums in which I have an interest so I share your good heart.

[Alan]

Quick update… I was able to successfully obtain thermal relief connections to the Vcc layer, which is fantastic. I’m super happy about that. I guess I still don’t understand why this works on one layer and not the other. The engineer in me is bothered by that because it makes me feel like the layer configurations must be different someplace. Unknowns are things I strive to quell, so I’m curious if there is any thought on the reason why it works on the one layer.

Anyhow, the most important thing is that things are working… Thanks for the quick and clearly thoughtful suggestions. Great group!

[paulvdh]

I’m very close now to the root cause of the problem.

I’ve extracted a clean version of your original zip file (again), and then: PCB Editor / File / Export / Footprints to new Library
This generates the file [Project] / Library.pretty / TE100_1734101-1_RECEPTACLE.kicad_mod

When I open this file in a text editor, all pads have their layers set to (layers * .Mask “F.Cu” “In1.Cu” “B.Cu”)

  (pad "" thru_hole circle (at 36.111 0) (size 3 3) (drill 2.6) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp 53322f45-bdd3-4673-964a-a7fe713f0d1a))
  (pad "" thru_hole circle (at -36.111 0) (size 3 3) (drill 2.6) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp a885586e-3a13-4754-ac24-36fc0d3fead3))
  (pad "" thru_hole circle (at -33.511 2.2) (size 2.8 2.8) (drill 2.6) (layers *.Cu *.Mask) (tstamp fc3bd02e-d505-4f55-8ffd-87e9afa8a0a1))
  (pad "A1" thru_hole circle (at -31.115 0.953 270) (size 1.524 1.524) (drill 1) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp 8ec1fa0d-d0b2-425c-8ad6-7d8adffba453))
  (pad "A2" thru_hole circle (at -29.845 2.858 270) (size 1.524 1.524) (drill 1) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp 28fd780a-bf16-4d03-a3d2-cd060b16e680))
  (pad "A3" thru_hole circle (at -28.575 0.953 270) (size 1.524 1.524) (drill 1) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp 9b2af444-83f6-4eca-b0ea-65018815da60))
  (pad "A4" thru_hole circle (at -27.305 2.858 270) (size 1.524 1.524) (drill 1) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp 84daae06-9e9d-4a56-84f5-639613e07126))

However, when I open that (exported) footprint in the Footprint Editor and look at the properties of a pad, then it claims to connect to All copper layers.

My interpretation is that this had nothing to do with either the GND nor VCC net. Somehow it got into the project that this connector does not draw pads on the In2.Cu layer at all. and a simple test confirms this. Even when I draw track to the A39 pad on the In2.Cu layer, then you can see in the 3D viewer that KiCad does not draw the pad on that layer.

I also wonder about all the other missing annular rings. According to the GUI, KiCad should always draw all annular rings on all layers, while according to the text in the file, it should at least also draw all annular rings on the In1.Cu layer.

Any update that causes the padstack to be reset to (layers * .Cu * .Mask)

  (fp_rect (start -38 4.05) (end 38 -4.05) (layer "F.SilkS") (width 0.12) (fill none) (tstamp 98aeffb9-e45a-44cb-b4fe-e3db274e15d3))
  (pad "" thru_hole circle (at 36.111 0) (size 3 3) (drill 2.6) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp 53322f45-bdd3-4673-964a-a7fe713f0d1a))
  (pad "" thru_hole circle (at -36.111 0) (size 3 3) (drill 2.6) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp a885586e-3a13-4754-ac24-36fc0d3fead3))
  (pad "" thru_hole circle (at -33.511 2.2) (size 2.8 2.8) (drill 2.6) (layers *.Cu *.Mask) (tstamp fc3bd02e-d505-4f55-8ffd-87e9afa8a0a1))
  (pad "A1" thru_hole circle (at -31.115 0.953) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) (tstamp 8ec1fa0d-d0b2-425c-8ad6-7d8adffba453))
  (pad "A2" thru_hole circle (at -29.845 2.858) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) (tstamp 28fd780a-bf16-4d03-a3d2-cd060b16e680))

What is the origin of this connector?
Can you recall how it happened that the pads were set to connect to In1.Cu, but not In2.Cu?

[paulvdh]

It also appears to be a bug in KiCad.

If the file data says (layers * .Mask “F.Cu” “In1.Cu” “B.Cu”) but the GUI claims All copper Layers for the pad connection, there is a clear discrepancy.

Also, when loading the footprint in the Footprint Editor, and then copying one pad setting to the Default Pad and then pasting those properties to all other pads, the pad stack setting gets reset.

[Alan]

Great research. If I can confirm, at some point I (or someone) should write a bug. I submitted one regarding phantom ERC faults that was introduced in the latest build (schema side) last week. At first they delayed it, but then others picked it up and it got elevated. I just got a github closure noticed so they’ve already got a PR for it and are merging into into main soon.

[Alan]

OK, I got a chance to read your last comment more carefully (sorry, doing my day job at the same time). It kind of confuses me (and I suspect you too) why there would be any references at all to the inner layers. I’d expect all of them to be “identical” actually, and now it is making me worried that perhaps I have an internal short on all of the connector pins. :(. Kind of odd.

But to answer your question… This is standard Tyco Electronics (TE) connector. The model is a 1-1734101-0 (sorry, the name for the connector in the footprint file is actually not correct). There isn’t anything special about the connector. It is just a staggered 2.54 OC connector.

As for the history of the footprint… I routed the entire board and didn’t have a problem. Then I realized that my original manufacturer (unknown) sample actually has reversed staggering from the TE version. As the TE is available, I needed to create a new footprint with the correct staggering, and then reroute the board. That is when all hell broke loose. I started with the original footprint I had from the unknown manufacturer and simply moved the pads around. That should have worked (I think), so I am baffled as to where the inner layers started to get defined in the footprint file.

Hopefully that helps

On edit… You know, it strikes me that any hard definition of layers here is probably a mistake. I think that there should be NO instances of:

(layers *.Mask “F.Cu” “In1.Cu” “B.Cu”)

Instead, I suspect that all of these should:

(layers *.Cu *.Mask)

[Piotr]

@Alan

It kind of confuses me (and I suspect you too) why there would be any references at all to the inner layers. I’d expect all of them to be “identical” actually,

My PCB manufacturer specifies different annular ring for outside layers than for inner.
Not long ago I thought that if hole is plated then to manufacture it a copper pads are needed at all inner layers. But recently I was told that plated hole can go through PCB even there are no copper around it at inner layers (may be not all factories can do it). Having there no pads lefts more sapce for tracks if someone needs.

[JuliaTruchsess]

@Piotr

Having there no pads lefts more sapce for tracks if someone needs.

Not only space for more tracks but also lower impedance of RF ground return
planes. Being able to turn off annular rings where unnecessary is a good feature.