Ran into a horrid problem today which was clarified by these articles:
The basic issue is a combination of the guidelines for building symbols with duplicate hidden names (i.e. stacking pins).
What I have is a regulator which has several pins to allow for higher current named Vdd and several pins as well named GND. As I want clean schematics, I followed the guildelines in the library thing to have 1 pin that was visible that showed the single net name that everybody was to be connected too, and then all additional repeat pins were named the same, made invisible, and physically stacked in the same place. With power input pins, this causes 2 problems. 1. it causes a “serious error” in the DRC because now it sees multiple power input pins connected “together”. Also, 2. The net name becomes global. This bit me as I had several different regulators which needed Vin from different sources. As Vin has hidden pins, this creates a global net name. All of these devices now are automatically routed together, and I have automatic hell. Same sort of thing happens when I am dealing with a split ground plane where I have a choke or similar arrangement between my analog chips with AGND and my digital chips with the equivalent DGND pins. The thing is that many of the libraries come with the pins labeled generically GND. As many of these devices have multiple stacked GND pins, I now have to watch to make sure that my analog chips don’t reach around and route to my digital ground screwing up my design.
I know that this is not a small problem and I am going to have to hand edit and watch for this particular issue. My current work around is to copy needed parts to a local library. From here, I relabel power pins Vin1, Vin2, etc. up to the number of chips I need. For multiplicities of a single chip, I create an individual copy of the chip multiple times. (The new footprint editor makes this much easier). Then I use a different copy of the chip for every iteration of the symbol that I need each with a different PINNAMEx iteration I have. This process, though obnoxious, works. If, perhaps in kicad6, we could do something like not use invisibility to immediately decide something is global, that would be HUGE. In the meantime, I am just trying to document collisions and bugs as I run into them.
It looks like your inquiry was addressed to me for some reason (I received an e-mail with your post.) But I think your question is a bit too deep for me. I do like to apply global labels, particularly because KiCad seems to produce ones such as “R27 pin 2”. Of course I do not differentiate between resistor pins.
Hey bobz, I think the reason that this was turfed to you was because one of the topics which clatified the issue you helped on. I think with respect to this problem, if there is a quicket work around, that would be great. Beyond that, if my ascertation is correct, then it dhould most likely be pushed in as a bug and or feature enhancement.
The issue comes up with parts that have multiple pins the same name. The worst case happens when there are multiple pins with the same bame which also corresponds to a power symbol which is in use. Either way though is messy. The problem is if you follow the kicad documentation on how to deal with this problem, the answer is to pin stack. This involves taking the first pin of a given name and placing it on the symbol visible. Additional pins with the same name are stacked on top of the first pin allowing for 1 connection in the schematic, but are made imvisible so as to not make the first pin hard to read. This unfortunately causes problems though with bnb power pins. 1. Causes a drc error as there are 2 power inputs connected to eachother and 2. The invisible pins are implicitly defining a global label which now gets autorouted affectively.
In my example I had 2 regulators connected redundantly from a pin that was labeled vdd though interestingly enough it was connected in this circuit to a voltage source other than vdd. Additionally on another part of the board was again the same regulator connected to another power supply. Kicad automatically connected all regulators to vdd and shorted everything out. I literally had to create multiple copies of the same regulator so I could label the power input to vin1, vin2, vin3, etc. So that at least as these sigbals were made global, they would be unique and hence not short together my seperate power nets.
I have a kludge that works. It is just that we have two different presumptions as to what hidden oins should to and what we should use them for colliding and seemingly causing problems. One group in the documents use hidden pins to deal with kicads inability to map many pins to 1 signal cleanly. As such this group suggests using stacked pins to mimic the desired roiting of a net to all pins simultaneously. Logic people though like hiding power pins, and having them automatically connect their and gates or whatever without having to make a mess of their designs with power connections. Finally, you have those that use the power port pins as a global tag by connecting hidden pins to get the power flags to act as they desire. Hidden though by its obvious nature doesn’t necessarily mean the desired outcome or use is global. This then can cause weird unintended consequences where kicad is automaticaalu connecting things that should not be connected. That is all.
This shouldn’t be this way. We can make kicad handle multiple pins referenced to one signal without hidden pin stacking and that would solve it. Seperating the attributed of being hidden as a pin from being global while keeping the current arrangement of stacking pins would solve this collision. Both many pins to 1 signal to a part and separating pin attributes of hiddeness and globalness would do it. I am just documenting that this is weird and acts in a non-intuitive matter which creates significant messiness in my world. This is how I know to get around the problem. Would it be possible to ask for something to change in the future to deal with these shortcomings? That is all.
Hidden power pins are a deprecated “feature” of KiCAD that @Rene_Poschl and the librarian team are working hard to get rid of from the official library (thank you guys!). As you well discovered it can cause unexpected problems and errors.
The solution is to make those hidden, stacked pins of type “passive” and only have the “power input” pin visible.
We never had stacked pins where the hidden pin was power input. The only thing we have is “normal” hidden power input pins that were used to avoid the need for a separate unit defining the power pins in multi unit symbols (mostly in symbols for the logic chips, the fact that nobody cares to fix them tells me they are no longer popular).
Ahhhhh- tried this with curses on my breath. The issue is that it would appear all attempts to label the circuit node is overtaken by the global tag. I even tried to attach a global power pin of a different label to break things up a bit, and it did nothing either. You and I think alike, but unfortunately, KiCad shot me down
Correct usually. All until you hide it. As soon as you hide it, it becomes a “node name” in the net node space. I believe (though I haven’t tested this thoroughly) that indeed it is a “global node name” in the net node space. This belief comes from the fact that the discussion with Scary thing with pin-names and net lists (or at least one of the quoted discussions from above) discusses the creation of power flags involves adding a hidden pin which is implicitly global. Whether this is true or not though, I have not exhaustively tested. What is clear though is that once you have a hidden pin in the pin name space, you get autorouting. In this case, he has no wires whatsoever. However, he can jump from a schematic with just a couple of parts to a pcb session, and get nets. I think that perhaps distilling this case to the most simplistic would absolutely be appropriate and is on my list for today. What I am seeing requires violation of the independence of the pin name space and the net node pin space somehow. That is what I’m yelling about.
—hmmm. I have looked into Power Symbols, and I do think they are my problem. Specifically, my understanding of how they create a global label through a mechanism in kicad to generate a net node (what I have read have said global in nature) which then ties to all other net nodes of the same name. With that said and in respect, you may have something else in mind that I am unaware. So while I have already looked, I believe a) you are right that indeed power symbols are my problem even in so far as what I know about the problem though what I know does not enlighten me with a workaround and b) there absolutely may be some other aspect of power symbols which may offer a solution to the base problem allowing an eloquent work around of which I am not aware. The problem is that I truly am not aware of such if it exists. Please point the way if indeed you are aware of something that I am not. (I will be replying to all comments that I have here including putting together some new tests, and showing some circuits and the like to help illuminate what I am seeing. Thank you for your response.
Yes! “normal” hidden power input pins… got it. All I ever thought about it myself until I ran into this and spent several hours poking this particular problem. What I have is a regulator that has a double input pin named Vdd, and a double ground named gnd. As such, and as a matter of common practice documented in the kicad common library document specifying the use of stacked pins, the first pin in the series of signal Vdd, which happens to be a power pin, is made visible. Additional pins are created, given the proper pin number, made invisible as to not interfere with the visibility of the first pin, and stacked on the same position. This wasn’t my doing and was done by the manufacturer/maker of the footprint. This is common practice though and I have used it literally hundreds of times myself designing symbol libraries. In this particular case, I have stacks of sensors, and other items working at many different voltages. I have 1.8v, 2.5v, 3.3v, 5v, and probably 5 other rails. You’ve got to love sensors! Anyhow, it just so happens that my regulator is not connected to Vdd. We are using Vdd otherwise in the circuit as a standard power flag (this may be significant, I don’t know and haven’t tested this part of it). Anyhow, after going through DRC, we pulled our parts over to PCBnew, and have been working on layout for awhile now. One of the issues though that was brought to my attention was for some reason the net connected to a certain pin was incorrectly labeled Vdd (thank heavens we saw it). Checking the netlist file, sure enough the nodes that should have in this case been explicitly labeled Vcharge were indeed lumped together with Vdd. The only mention of Vdd on any of those pins in the net of question were the pins as described. From my reading, I thought that it was (and yes this is an assumption based on my reading which is my bad if I was wrong) the hidden nature of the pins added to a standard power flag which triggered it to be a global net name and so act as we expect power flags to act. One of the salient features of the headaches being produced is the propagation of names from the pin space into the net node space causing net names and netlists that have been improperly simplified (multiple nets shorted together). This isn’t a problem if the net name that you are shorted to is the same as where it actually is being connected. I think this is why I have never been bitten before. You have to have a non-unique name being hooked to a net which is not the same as it is. Additionally, if this requires hidden pins in order to cause the contamination of the net name space, then I have to admit, this wouldn’t be a very common combination of things even with the number of designs that I have worked.
The reference to Vdd in the net in question is on the pin of a part. Specifically, we have both visible and invisible pins involved. Additionally, the circuit which our circuit of interest is being shorted too does have a Vdd flag. As such, there is a power flag involved.
What I absolutely know is that the behavior of auto-routing with hidden pins is very similar to this in that we have a power pin that is hidden being auto-routed to a power flag of the same name. In fact it is identical as far as I can tell. We don't even need to know that the hidden pin happens to be stacked. That is only why it was done. This is a common practice to deal with multiplicities of pins to a single signal of which power pins for current carrying and other reasons are commonly designed by the manufacturers in this way. i.e. multiple vdds and multiple grounds. The salient fact is that this hidden pin has a name of a net which I -don't- want it to route too. The work around is duplicating the regulators for as many regulators as I am going to be using (which this design uses something like 10 plus regulators), and forcibly change the names of the power clusters so that they all have unique names. Works, and honestly with the work that has gone into the symbol editor is not absolutely horrible. But it is a hack that I would prefer not to do, especially if there is a normal way to do things. Will be building and posting more information including a circuit to demonstrate.
I don’t believe the PWR_FLAG causes any label to be global. I think of it as a way to tell the ERC to NOT give an error when power comes from an external source. If there is a side effect related to hidden pins, I am not aware of them.
Global labels do have priority in node names over wire labels. This is not a surprise conflict, just a priority.
I suggest you experiment with some simple examples. You are describing this as an interrelated complex problem. While this may be true, you should fight only one battle at a time.
Make 2 new symbols, one with NO hidden pin and one with. Try a few things and see what the results are. If there are significant differences, it may be a bug, and this will provide good evidence.
As @iabarry said, net names are determined by a priority system – there are not separate namespaces.
From lowest to highest priority:
Normal component pins
Hierarchical sheet pins
Whatever the highest priority “possible name” is on any particular node will determine its net name. Options 1-3 are “local” names, meaning they will get prefixed with the hierarchical sheet path in PcbNew. Options 4 and 5 are global (of course all global labels are connected across sheets, but also all power pins are as well). Global nets do not get any sheet path in PcbNew.
ummm-- power_flag general. Not the specific power-flag symbol which specifically isn’t global. I was using the term generically to be open to labeled power symbols. Perhaps I should have used the term power symbol (though technically power_flag is a power symbol). Ugh. In this case, Vdd. I apologize. I was not clear. Read generic labeled power symbol which is global. I don’t know what the proper word is. For this example specifically, read Vdd power flag.
To make it easier to understand, this symbol is not really special. It is just a single pin with electrical type power output. In addition the symbol is setup such that it does not expect a footprint nor is it exported to the BOM. (both these are handled by prefixing the reference with “#”. Setting “this is a power symbol” now also guarantees that the “#” is added and ensures the symbol is shown by the “add power symbol” dialog)
Cool, I have been looking for this. Thank you. I need to sit and stare at it a bit before its meaning will penetrate, but this is very helpful. So, we had a name of vdd from a pin name which should have resolved as /sheetname/vdd. But that wasn’t what I got. I got vdd as my net name (verified in circuit.net). Made sure I refreshed my netlist, and rechecked. Still vdd. hmmm. Still, this is invaluable. Thank you. I need to layout a circuit demonstrating the results in question.
Yes, sorry I could have been more clear about that. There is nothing hard-coded special about PWR_FLAG, it just happens to be the only power symbol in the default library that has the Power Output type, meaning you can use it to tag nets that ERC would not normally know are properly powered.
The rest of the power symbols are all defined as Power Inputs which may sound strange at first, but the reason is that ERC will complain if you have more than one power output connected together (which makes sense – it could be a design error). So, if you have a regulator that has a power output pin, and you wire that pin to the +5V power symbol to distribute 5V through your schematic, the +5V symbol needs to be a power input so that it does not conflict with the regulator output. ERC will be happy because it sees the power output pin on the regulator driving the whole +5V net.
On the other hand, if you have power coming from an off-board connector, your connector pins are probably passive (not Power Output) so you could use PWR_FLAG to silence the ERC warnings about the net having no power source. This will also happen if you insert a series resistor between your regulator output and the +5V symbol (for current measurement or whatever).