As i have written above: only invisible power input pins make labels. No other pin type/visibility combination does this.
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There are two ways a pin can become a global net:
- If it is type Power Input and is invisible
- If it is type Power Input and the symbol it exists on is a power symbol
A power symbol is simply any symbol that has this box checked:
That would be news to me. Are you certain this is the case because if so then we can update the symbol library already for v5 to get visible pins for power symbols. (also i would need to update my tutorial)
This is beautiful Craftyjon. This is describing exactly what I have been discussing. In my particular case, I actually had 2 collisions. I have 1 collision with a power flag colliding with an invisible power pin (done due to stacking), and I have a separate collision of the invisible power pin on 1 regulator with the invisible power pin on another regulator shorting out different power rails.
This is certainly the way it works in nightlies but I would have to go back and verify with V5. I don’t remember this being a change from V5 to the new connectivity algorithm.
I just tested this in v5.1.6 and you are indeed correct. I think i will update our power symbols in the official lib to have the pins visible and hide the value field instead (as the pin name is what really defines the net name not the value field).
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Okay, here we go…
Demonstration Regulator:
Demonstration Circuit
And finally Demonstration net list: … tried, but not allowed now.
Anyhow, it ties the vdd pins on the circuit to the power source connected to the resistor.
Got the net list, and it does show it. Previously it labeled the net VDD which I think was clearer to my mind. This one through me for a loop as the combined net was named +3V3, however if you look, you will see (node (ref R1)(pin 1) as the bottom node of that net which creates the short. Additionally, you see the second collision as U2 Pin1 and U2 Pin2 are also nodes in the netlist. Notice that those are connected to the 5V power flag.
Similarly, to highlight the second collision, or catastrophic side affect if you would prefer, we can remove the global power symbol Vdd and associated resistor, and look at the resulting circuit and netlist.
And then we have the resulting net list:
Note that in the net(code4)(name +3V3) we have both nodes from ref(U1) and nodes from ref(U2), i.e. again though there are no explicit connections, we have a routing caused by the name of the regulators which is shorting the net list. It is not just the nature of the Vdd power flag existing as a global, but indeed, the regulators themselves act as global flags which will connect to other iterations of the same component used other places in the circuit.
Summing up solution, the issue causing the collisions particularly is the use of hidden power input pins. The way to eloquently solve this problem per Der Rule is to have the first instance of a power input pin visible as a power input. This will cause the DRC to correctly apply the rules for power input net checks. Additional hidden pins need to be made something like passive. (suggest specifically using passive though others which don’t cause the throw of a global net would also work). Take these passive pins, hide them, stack them on the original power pin, and whalla… Magic.
Now for pictures… Again, thank you Der Rule:!
Note (net(code 4)(name +3V3) contains just nodes refU1 and (net(code 5)(name +5V contains just just nodes ref U2.
There is no shorting together of networks anymore… Yeah!
Additional small note: In these pictures I did not truly stack the pins for reasons of making the different labels and attributes clear. As such, there is a one pixel difference in the location of the pins. This then required that I extend my wires on the circuit to force what in a proper pin stack would be automatic. That is why there is a short jumper wire in the schematic to what is seemingly nowhere. It is actually to give connectivity to the invisible pin. In practice, actual stacked pins would be right on top of one another alleviating any reason to jumper to invisible pins. Thanks all for your help.
Overall, this is a landmine of unintended consequences. It is something that I will have to be aware of and I think we have documented fairly well. Additionally, for at least the time being, we have a wonderful work around. There was some discussions as to possible future work that may make things smoother in this regards and I look forward to when that is available to test. Thanks to all of you for your help.
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