I recently moved to KiCad 6 and upgraded my projects from 5.1.2 to 6.0
Now I am trying to generate Gerber files and noticed some options are missing in KiCad 6.0
I am using this instruction to create the gerbers
and noticed the Exclude PCB edge layer from other layers and Exclude pads from silkscreen are no longer in KiCad 6.0
So is there any way to activate them?
Think the terminology has changed slightly.
Thanks for your quick reply.
So you mean by enabling Plot Edge Cuts on all layers both Exclude PCB edge layer from other layers and Exclude pads from silkscreen will be enabled?
I see Subtract soldermask from silkscreen is available on both versions
This was a confusing pre-historical fossil. It was needed because before fire was invented silkscreen was used so that pad area was covered. It was then used as an assembly guide. That option existed so that it could make sure KiCad pads didn’t have the Silk layer active in footprints while plotting. It’s not needed because the Silk layer isn’t active in footprint pads in the current KiCad libraries.
This means that silk isn’t printed where there is no soldermask in the physical board. This (usually) means pads, too.
WARNING! (@John_Pateman) You screenshot shows “Use extended X2 format…” + “Include Netlist attributes” + “Disable Aperture macros…” checkboxes set in such a way, that contradicts this: Post-v5 new features and development news - #333 by eelik post.
I always set these three checkboxes according to the link above and have no problems. Actually, I have made a mistake with these checkboxes (don’t know how I configured them at that moment) a month ago and had problems with JLC:
- There were no thumbnail of PCB I am going to order, as usually is shown in their webpage (first bad symptom);
- Solderpaste (stencil) screenshots looked weird (flower-like pads instead of rounded rectangle pads) after JLC review, so I had to reorder JLC order with reexported gerbers with settings from the link above;
I think these settings are still problematic, and your screenshot should be updated in order not to cause faulty orders for users. Please excuse me if I am not correct.
I think this is a big issue (potentially causing reorders at the fabhouses), and should be clarified by developers, or JLC team…
Solderpaste layer, as seen at JLC with wrong gerber settings:
There were some experiments by @atommann here which suggested that the error was not repeatable with the X2 option set. There was also a problem with the JLCPCB viewer which showed artefacts although the boards came out OK. The discussion was from January 2021 and I seem to recall there were some changes to the rounded aperture generation code since then.
From KiCad side yes, there were changes, but seemingly not at JLC side. Screenshot of solder stencil is from JLC order at 2021-November. PCBs were OK (no questions from JLC, no issues when boards arrived), but stencil service was problematic, regenerated gerbers only for them…
Hi, I hit my head that night because I did not get the CPL File for SMT Assembly uploaded at JLCPCB. The file kept getting errors until I created the file by hand. JLCPCB doesn’t like comments in the files, furthermore the columns should be sorted correctly.
So Add BOM File JLCSMT => Column 1 = “Comment”, Column 2 = “Designator” and the 3rd column = “Footprint”.
Add CPL File for SMT Assembly => Column 1 = “Designator”, Column 2 = “Mid X”, the 3rd column = “Mid Y”, the 4th column = “Layer” and the 5th column = “Rotation” .
“Mm” must be appended to columns 2 and 3.
The 4th column must be “T” for F.Cu and “B” for B.Cu layer.
I spoke to an employee of JLCPCB again earlier. It was about “Mid X” and “Mid Y”. See image:
If I understood everything correctly, the created component position file is wrong, because half the component size is not included.
U1 MCP6022 SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm 21.8060 21.5000 90.0000 top
L = 7.4 mm
B = 5.4mm
X = 21.806 mm
Y = 21.5mm
Mid X = 7.4 / 2 + 21.5 = 25.2
Mid Y = 5.4 / 2 + 21.806 = 24.506
I left JLCPCB on Oct. 6 2021.
You can send me the Gerbers rendered the flower-like pads, I can investigate. I guess something is wrong in JLCPCB’s code (previewer). My email is firstname.lastname@example.org
If you run KiCad in Linux, you can use the method in this article: How to Generate BOM and Centroid Files from KiCad in Linux - JLCPCB: Help & Support
I think there are some euivalent plugins in Windows too.
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