Is it too close though? for SMD resistors the outer red is at the grey border and these I may have touching one another. I thought the inner/outer red defined the minimum gap?
The outer red defines the solder mask cutout. It does not give direct information about component placement.
Component placement is not only limited by electrical restrictions but mostly by the assembly machines. The solder mask gab is normally a lot smaller than the gab needed for the assembly machines. (Again the nominal IPC specified clearance between pads and bodies of different components is twice the courtyard offset -> 0.5mm)
In fact looking at the part to the botom left i think you might have quite large settings for solder mask clearance. (Check what your manufacturer is capable of creating and set this up accordingly.)
Moving the vias off pad has proved quite a struggle. Am I right in saying a micro via can only go one layer deep? I can’t make it to go from layer 1 to 3 and that means I’m having to use standard via’s in some places as you can see in the picture below. It’s likely (IMO) to prove a problem.
If I could I’d micro-via the lot but skipping layers doesn’t appear to be possible.
A.
You have silkscreen text on pads and under smd components, it shouldn’t be there, especially on pads. With such a tight layout there’s no room for silkscreen texts and they must be left out.
You could read the relevant part of https://kicad.org/libraries/klc/#_footprint_guidelines, find “F5 - Layer Requirements” there.
The Fab layer should have the physical simplified outline of the component, dimensions are as expressed in datasheet. CrtYd should have necessary space added for each component, inside which there should be no other physical component. If I have understood correctly the courtyards themselves may overlap, just like with pad/track clearance areas. In real life manufacturers may be able to assemble boards which violate courtyards. Courtyard layer is for the pcb designer, not for manufacturing.
It’s a bit strange that you have components which have different silkscreen and 3d-image dimensions. You should be sure which one is correct. Actually you should always check the footprints against datasheets if you haven’t used them before.
Err yes, they were just for my reference and won’t be printed on production.
By and large I’ve respected the courtyards, other than the SOT 323. You can see how in the picture below. The 3d render of the SOIC-8 has a small bug but perhaps it’s fixed as I’m on 4.0.6.
My main worry is the size of the standard VIA’s. I’ve got three which are in-between a 0805 resistor and it smells bad.
Just remember: A pcb looks a lot larger on your screen then in person. (You will hate yourself if you ever have to repair the pcb or get a measurement tip in there.)
If you are not limited by external requirements i would suggest you give yourself a bit more space in general.
It’s for the cycle market. Size and weight is everything!
It won’t need to be repaired, too small for that. The sub-circuits have all been built on breadboard previously so it’s a case of whether the PCB can be produced and assembled without error.
Still can’t crack the micro-via’s between layers 1 and 3. Rather out of space!
That is some tight placement! If you’ve got concerns about assembly, I would move those components apart. Although you don’t plan to repair it the SMT shop might need to do some touchup to keep yields up.
There are several other ways to save space:
You can keep the vias in the pads but they will need to be filled to prevent solder thieving (as @eelik mentioned).
Some of the individual components can be replaced with array components.
Move to smaller components - 0402s or 0201s.
You can always specify a thinner stackup than the standard 1.5mm.
Looking at the pictures I’m not sure if you already have tracks under smaller components, but it’s possible to do that. You can even spread 0402 pads apart a little bit and fit 0.15mm track there with 0.15mm clearance (if the manufacturer can do 0.15 track it can do 0.15 clearance, too, I guess). It may give many new routing possibilities. I would avoid placing vias between a component’s pads, though, unless there’s plenty of clearance and no danger of tin contact. Sometimes a via may be exposed a bit even if it’s covered with solder resist.
If you had done any amount of research over the last three days you would have easily learned that micro vias typically only span one dielectric thickness due to aspect ratio limitations. To span multiple thicknesses they need to be stacked. You need to check with your fab if they can even do micro vias as well as stacked vias. Micro vias as well as blind/buried vias and via in pads will all likely incur significant additional charges.
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My understanding now is if I place a via from layer 1 to 3 it’s actually a blind from 1-3 and a buried from 2-3?
My fab company indicates I’ve used buried vias but I can’t see how otherwise.
They can do 0.15 tracks and I’m using them where necessary. I’m already routing through components as shown. There’s not many passive components and going to 0402 or lower is not realistic for power handling.
A cost of a prototype board due to the micro-vias and poss blind/buried was just re-quoted at +400%!
I just asked my dad to have a look at this and he says - hard to give any good advice as we would need way more information what this thing does and what the characteristics of some of those parts are. He also says - the designer should know what to do and how to get there, as otherwise he’s in over his head with this anyway and there is nothing outsiders can do really without way more information/disclosure.
- what does this circuit do (do you have big power or high speed signals there)?
- there is a couple of things that stick out which make no sense whatsoever:
- you use 0603 and 0805 or bigger willy nilly
- why the two THT diodes in the center?
- all those SOIC8 housings (can you change them to smaller ones?)
- SW1/2 can be thinner versions
- what’s up with the big THT holes in the vertical center of the board?
- what’s up with the THT Jxy holes on the right of the board, can you amalgamate them into one thing/connector?
- if that 4 pin connector on the right is a programmer connection there is smaller ways to skin that cat
- what’s up with the fan-out on that IC? Why all that space wasting? And what is the thermal pad underneath it for without vias?
- whats up with that empty space to the left?
- it all looks so uncoordinated, no sub-assemblies recognizable, which would make packing/routing easier, example what I mean:
- have you thought about both front and back being used as assembly sides for components?
- maybe your circuitry can be optimized as well, but this would then start to become more of a paid job if one would look at that…
We’re no strangers to packing things tight, but it looks different to what you’re doing (still handsolderable by my dad with a stereo microscope, the Rs and Cs are 0805):
Some general advice:
- assemble functional subgroups OUTSIDE of the board
- move/rotate components in these assemblies until they are as tight and optimized (short paths) as you can do
- then move the stuff into the board envelope and see what you can keep and what needs to be re-aligned to work with the other parts
- be sure to know beforehand where interface components (connectors, switches, LEDs) need to be and how flexible you are with them
- if you care about size, find the smallest stuff you are still able to handle (JST 2.0/1.5/1.0 come to mind for example, I can crimp JST 1.5 contacts worst case for prototyping, it’s a PITA though)
- consider stacking boards… having 0.6mm boards stacked over each other is really easy if you keep the components flat on one of them
- consider housings with 2 times the component in them for the same footprint size, for example there are 2xPNP/NPN or even mixed NPN/PNP transistors available in SOT23-6 housings or smaller in SOT363, which would (I assume the SOT23’s you got there are something like that) ideally reduce their footprint to 50% of what you got now…
You’re on your own for the time being.
Good luck.
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Hi, answers below.
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it’s a bicycle dynamo power system, there are effectively 5 voltage levels on layer 3.
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I use 0603 if poss but 0805 is required for a) wattage (FET driver circuits for several PWM’s) and b) accuracy - 0.1ohm @ 1% tend to be 0805 or are expensive!
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THT - AC zener clamp. Required to be there as will heatsink off huge capacitors on the rear. Generally they aren’t used much as the voltage they engage at is quite high.
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SW 1/2 - can’t get smaller, they’re tiny as is!
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Big super capacitors
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Spade connectors (3 pair), can’t change them.
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No, it’s a USB. The three small pads near the MCU in the top left are for programming.
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I think you’re referring to the fact the micro-vias are not on the pins. Due to using 0.15 tracks they need fanning out to place the micro-vias. The problem is exasperated by the hole-throughs (see attached).
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That’s for a bluetooth antenna.
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It is, but really there’s several sub circuits being driven from the MCU; 7x PWM, a buck, USB detection/switching, several voltage/current detection circuits. These are using 1 of 3 main voltage supplies. Oh, and there’s active rectification as well. It would be great if it were a simple input-process-output but alas it is not. The sub circuits are contained but the hole-through’s has made some routing… interesting!
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originally yes, but I was told double sided SMD has reliability problems.
Cheers,
A.
Most the IC’s are dual FET packages. Current monitors are "dual"ed up. It’s possible I could have made some of the SOT-123 transistors dual or even quad packaged but that but have made for long tracks between sub-circuits. I think I’ve already stretched the tracks to the limit! 
Why is that?
What was the reason given?
I would expect a lot of repeated patterns on your layout then, but can’t see them really?! 
Not available as SMD?
You handsolder them anyway - just extend the pads for that.
Not as SMD available either?
Sames as for the supercaps…
And those SOIC8 housings, dual FETs or what?
Not available in smaller packages like powerpack 1212-8 or similar?
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Dual side SMD - components desolder when the opposite side is heated.
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Repeated patterns, that was the intention, but track congestion and hole-through’s got in the way. Those SOT23’s are NPN’s, except the ones near 3 o’clock which are P-FET’s. Dual FETS tend not to have the performance characteristics which is the case here - they Rgs on @ 2V. 9 o-clock around the 1 o-clock SOIC’s are dual P-channel, low Rgs of about 2V again. The reason for using them is a 40V Rds rating. Those zeners kick in at about 33V.
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100F @ 5.5V …
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5W. I did look at 5W SMD’s but then I’d need to use the board for heat dissipation if it comes to it, and that’s a problem because it’s small and covered in parts that like to fall off when they get hot. This also applies to the zeners themselves. They’d probably fall off first and destroy the other circuitry.
It may look like a pile of shit, but the board has a end-to-end typical efficiency of 96% or higher while operating down to 1V. Some thought did go into component selection to achieve it. Originally I was going to pay the PCB fab company I use to design it - they said it was impossible and hence I’ve had to learn PCB design myself. All fun!
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Are you planing on constantly dissipating 5W or is this for short therm over voltage protection?
If it is the former there must be a better circuit that is more energy efficient! If it is the later then i don’t think you need to worry (that much) about heat dissipation.
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As @Joan_Sparky has already stated, it is hard to give specific advise regarding this layout based on the little information we have. With a processor, USB, bluetooth and 7 PWM channels surely this board is more than just a dynamo power system. However, from the images you have posted, it is a rather crude layout. You claim you are using the thinnest tracks you can but in most areas you have enough clearance between tracks to run several more. Component placement is not very optimal and there are many examples of vias, even via in pads, that are simply not necessary. There are tracks at various angles when there is no need. There are tracks that don’t meet other tracks but extend past. Then there is the ref ids under components with silkscreen on many of the pads. In terms of pin count this board is not that dense, I don’t know why you think you need micro vias, or even via in pads but it would probably be more cost effective to simply add 2 more layers.
LOL! Who told you that?
Then I would definitely not be using that fab.
You certainly know your FETs.
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Adding more layers still requires blind/buried vias to get to them.
If someone can explain how to fit standard via’s with this level of tracking I’m all ears!
Like this?
The fab naturally needs to be able to hit the copper of those via pads, jitter shouldn’t exceed 2 mils. Clearance is not absolute max (12 mils), but close to it… so all still within the standard of what they usually are able to do.
Really really cheap ones can’t do that afaik, or if they claim it, the output will be crap.
You should order a sample from them to make sure they can do it anyway.
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