So, the last time I created a PCB was with Crocodile Clips and PCB Wizard on Windows 3.11. I’ve now made a PCB which squeezes in several circuits controlled by a MCU. Space is tight and through-hole components made it quite difficult to keep to the ideal PCB size of less than 50mm^2.
At first I was using 2 layers but it became apparent the connections would be far greater. The standard VIA’s were taking up too much room and I opted for 4 layers with micro vias;
top, general smd
signal - mostly for MCU connections
power - currently unused, but I have 4 voltages which need to be transferred around the board
bottom - GND, less abused as time went on, used signal instead.
The MCU tracks are 0.15 as this was the only way to fit it all in. Standard tracks are 0.25 and power should, if manageable, be 0.5. I will need to via or micro via to layers 3 and 4 at times to make these work.
How does all this sound? I’ll post some pictures.
One immediate question is how to do a micro via from layer 1 to layer 3? I’ve only been able to make it work from 1 to 2.
Cheers,
Andrew
Picture 1: rear, shows around the MCU (top left) where I’ve oped for links on the signal layer, whereas else where I was using standard vias. This became a problem as the vias remove too much of the bottom layer and the GND’s then don’t connect.
The remaining rat’s nest is for 4 voltage levels. There’s no pattern to them unfortunately. My intention is to use the third layer for these (plus a bit of layer hopping).
My only advice is that 4-layer board increases the board manufacturing cost. It there’s any way to create the board in 2 layers and less than 100mm x 100mm then it could save money on that cost.
You still have to watch minimum width spacing (for copper, they should be 6mil width and 6mil spacing). But especially watch out for solder mask spacing, as some manufacturers will remove soldermask less than a specific width, and that width is sometimes different than copper width/spacing depending on manufacturer.
You may get into problems with vias inside pads unless they are hand soldered. The paste may go into holes and the parts will not have good connections. Sadly this doesn’t make your work any easier, you have to get more space for the vias…
I’ve found a bug with eeschema (as far as I can tell).
When running a GND like this the GND isn’t actually attached and no ERC warning is triggered. I only noticed by chance by the labelling of the PCB net. It only occured on one of the examples in my schematic, the rest are correct.
Yup, I expected it to work like a component and say the power input pin wasn’t connected. Had a look for a “Hightlight Net” feature but couldn’t find it.
Hi “eelik”, can you confirm I need to move those two via’s in pads or are they OK?
All my vias are blind from layer 1->2 or 1->3 or through-hole. Optionally I can do them all as micro’s, perhaps it’s cheaper to fabricate if they’re all the same…
I’m not an expert at all so I don’t want to give any definitive answer. It depends at least on the hole size and the paste used. Through-holes are of course more problematic. Depending on your manufacturer it may be possible to plug vias (I wouldn’t recommend tenting the solder side). Maybe you could contact your board manufacturer and ask them about the options and if they see this as a problem.
IMO your layout looks too abitious. Vias in pads; components are touching each other, which means the automatic assembly phase may be impossible or very difficult. Some amount of courtyard area should be respected (avoiding overlapping silk lines isn’t enough). And still you have so many unconnected lines.
It’s only the 8 pin chips that are touching, that appears to be a model issue as it’s drawing outside the silk line area. The only place I have violated the silkscreen boundary on occasion is with the SOT-123.
The silkscreen is not really that important. Make sure the CrtYd area is never violated and the CrtYd is drawn acourding to your requirements. In the official lib we use a courtyard offset of 0.25mm (for devices > 0603).
The only place where there’s much violation is the SOT-323, but only with pads. I’ve stuck an example below. For this device it appears the blue outline is more appropriate?
The courtyard is always measured relative to the pads and body depending on what gives a larger area in this direction. (Currently most components in the lib use a single rectangle around the part, newer IPC standards allow for more complex shapes that follow the outline of the body including it’s pads more closely)
I fear this is violated at least on the right side of pad 3 of Q22 (Pad 2 of the next component is way too close)
There you might even have problems because there will be no solder mask in between.(Minimum width settings)
