Thanks All for your feedback.
Yes, they are all GND connections and I draw a track from the pads to connect them with other planes using the vias.
I think track widths are 0.0254 per tutorial I am following but I don’t have a problem to make them wider.
I have the four layers but I was limited the number of media files I was able to upload because I am new in the forum. Here is other screen shot.
Wow! Is that 0.0254 mm or 0.0254 inches? It looks more like the first one…that is not manufacturable so far as I know. Another poster was just inquiring about 0.15 mm. 0.15 mm (solder mask width) is tight but seems to be do-able. I have never heard of a track width less than 6 or maybe 4 mils = 0.1 mm.
Don’t PTH pads have Cu on the inner Cu layers also that can be connected to tracks or zones there? Then you don’t have to start from the F or B.Cu layer.
This FAQ explains how you self promote yourself to “Basic” from “New User” so you are able to post multiple files.
The PCB guidelines I am reading recommends to leave all the components as much as possible in the outer layers of the pcb, specially SMD components. is this what you mean?
I will do, thanks for the suggestion.
My bad, that is the resolution (i.e., zoom in) of the pcb file. The track width is the standard 0.1524 mm.
FWIW, I generally use 0.2mm as a minimum track width, and a 0.6mm via with 0.3mm hole as a minimum (0.15mm annular ring) – this is easier for fab houses to meet without charging extra.
For a board that is not particularly dense I use 0.25mm tracks with 0.8/0.4mm vias.
When I do a dense board I use 0.125mm tracks with 0.5mm vias with 0.2mm holes, but this usually costs more. Check with the standards the fab house publishes.
I also don’t like running a thin track into a PTH hole that will get soldered (with a socket or thru component). It just does not seem like a good idea and you are asking for the soldering heat to expand and contract perhaps leaving an intermittent or severed connection to the tiny trace. I use a fat trace (0.5 or 0.6mm) as a transition. Kicad now has teardrop options though I have not tried them.
There is not much resolution in your screenshots, and I can’t really see what you have made, but it looks like you did not draw any copper zones on your inner layers. Just changing the name of a layer to “VCC” or “GND” does nothing to connectivity. You also have to draw the copper.
Edit: teletypeguy also already mentioned this:
Also, On a 4 layer PCB, it’s usually better to assign both inner layers to GND, and then route the tracks with (fat) PCB tracks.
Hi Paul, thanks for the feedback. Yes, I name the layers with these names but I also draw the copper zones in the respective layers. I will upload the pcb file when I have access to it.
I can’t upload the pcb files but here I have attached a screenshot of the scheme wiring. I was wonder if the problem is in the way how I define the global labels and KiCad is still trying to join the components in the pcb files.
My guess is that you haven’t associated the copper zones on your inner layers with the GND and VCC nets.
Naming the layers doesn’t do it; the layer names are only for user convenience. Copper zones must be associated with their nets or they’re just unconnected areas of copper. Once you do that all your vias and through-hole pads should automatically connect with the inner layer copper zones.
The corollary to this is you don’t need vias to connect a through-hole pad to an inner copper zone if the hole passes through the copper zone. This will happen automatically.
Another possibility is that you haven’t filled the zones before running the DRC. Recent versions of KiCad does this automatically more often than it used to, but it’s something to try. Hotkey: “B”
I am quite certain no copper zones have been defined at all yet. In none of the screenshots posted by Juan_Carlos_Cuevas_B I see the tell tale hatched borders of zone boundaries.
@Juan_Carlos_Cuevas_B Do this:
Some things about your schematic:
Is the global label VCC the same net as the power symbol VCC? Don’t mix the two. A power symbol already creates a net.
I2C wires, consider using a bus.
Zig zag wires, GND and VCC going sideways or up instead of down and vice versa, symbols not positioned neatly, ugh! Spend time making your schematic neat, it’s you who will have to read it later.
Power symbols act very much like global labels, but I agree that it is a bit “messy” in the schematic to mix them. You can check wheter KiCad recognises the connection between those two with the highlighting function (Backtick key, between [Esc] and [Tab] on keyboards with US layout).
@paulvdh and @RRPollack you are correct. I did define the copper zones at the beginning. However, I updated the scheme and the net list, and it seems that every time I do that I have to redefine the copper zones. Anyways, I redefined them and it is working fine now. I will check all the other recommendations you did. I have spent several hours designing this PCB but I still have to learn a lot of fine details.
Thanks all for your help,
