Four Layer PCB Design problem with connection between layers in Kicad 8.0

Hi All,

I’m currently working on designing a four-layer PCB (Signal->Ground->Vcc-Signal) for magnetic measurement purposes. While I’ve made good progress with the design, I’m encountering an issue flagged by the Design Rule Check (DRC) that states:

Error: Missing connection between items

Despite creating vias to connect between the different layers (e.g., using Micro to connect the Signal->GND and Signal->VCC layers), it seems that KiCad is not recognizing the connections between the Signal and GND layers.

I have attached screenshots of my PCB and schematic files for reference. Any guidance or assistance you could provide to resolve this issue would be greatly appreciated.

Thanks in advance for your help,


It looks to me that these are all GND connections. Surely you need to draw a short track from the pads going to a via that burrows to the GND layer?

I don’t see a ground or vcc plane, just top/bot layers. Do you have zones defined for those on the inner layers? A full plane for vcc is generally not needed when you can route power as a tree. If the ground plane was there the through-hole pads would get automatically connected during zone-fill. The smt pads need a via dropped adjacent to them.

One possible 4-layer stackup: top has most signals and most or all smt pads, layer 2 is solid ground plane (possibly divided into digital and analog sections), power tree is on layer 3 and/or bot layer, and bot layer has more signal routing with extra signal jumpers on layer 3 as needed. When defining the ground zone on layer 2, check all layers to flood-fill ground in all extra spaces on all layers, then add stitching gnd vias to ties the grounds into a tightly-connected structure. Layer 3 can also be used to embed noisy spi buses and such between ground planes above and below.

I am not sure what I am looking at. I think you have extremely narrow tracks, but I do not have a good reference to tell.

I should mention that I generally like to use tracks which are almost as wide as the connected pads wherever there is area to do so. Based upon the footprints that you are connecting, I think you could increase your tracks to at least 0.3 to 0.5 mm width. At least it would be more clear as to what is a track and what is a ratsnest line. That change might possibly resolve your issue(??). Just an educated guess…

Thanks All for your feedback.

  1. Yes, they are all GND connections and I draw a track from the pads to connect them with other planes using the vias.

  2. I think track widths are 0.0254 per tutorial I am following but I don’t have a problem to make them wider.

  3. I have the four layers but I was limited the number of media files I was able to upload because I am new in the forum. Here is other screen shot.

And my scheme file.

and the short track from the pads. Sorry for the multiple answers.

Wow! Is that 0.0254 mm or 0.0254 inches? It looks more like the first one…that is not manufacturable so far as I know. Another poster was just inquiring about 0.15 mm. 0.15 mm (solder mask width) is tight but seems to be do-able. I have never heard of a track width less than 6 or maybe 4 mils = 0.1 mm.

Don’t PTH pads have Cu on the inner Cu layers also that can be connected to tracks or zones there? Then you don’t have to start from the F or B.Cu layer.

This FAQ explains how you self promote yourself to “Basic” from “New User” so you are able to post multiple files.

The PCB guidelines I am reading recommends to leave all the components as much as possible in the outer layers of the pcb, specially SMD components. is this what you mean?

I will do, thanks for the suggestion.

My bad, that is the resolution (i.e., zoom in) of the pcb file. The track width is the standard 0.1524 mm.

FWIW, I generally use 0.2mm as a minimum track width, and a 0.6mm via with 0.3mm hole as a minimum (0.15mm annular ring) – this is easier for fab houses to meet without charging extra.

For a board that is not particularly dense I use 0.25mm tracks with 0.8/0.4mm vias.

When I do a dense board I use 0.125mm tracks with 0.5mm vias with 0.2mm holes, but this usually costs more. Check with the standards the fab house publishes.

I also don’t like running a thin track into a PTH hole that will get soldered (with a socket or thru component). It just does not seem like a good idea and you are asking for the soldering heat to expand and contract perhaps leaving an intermittent or severed connection to the tiny trace. I use a fat trace (0.5 or 0.6mm) as a transition. Kicad now has teardrop options though I have not tried them.


There is not much resolution in your screenshots, and I can’t really see what you have made, but it looks like you did not draw any copper zones on your inner layers. Just changing the name of a layer to “VCC” or “GND” does nothing to connectivity. You also have to draw the copper.

Edit: teletypeguy also already mentioned this:

Also, On a 4 layer PCB, it’s usually better to assign both inner layers to GND, and then route the tracks with (fat) PCB tracks.

Hi Paul, thanks for the feedback. Yes, I name the layers with these names but I also draw the copper zones in the respective layers. I will upload the pcb file when I have access to it.

I can’t upload the pcb files but here I have attached a screenshot of the scheme wiring. I was wonder if the problem is in the way how I define the global labels and KiCad is still trying to join the components in the pcb files.

My guess is that you haven’t associated the copper zones on your inner layers with the GND and VCC nets.

Naming the layers doesn’t do it; the layer names are only for user convenience. Copper zones must be associated with their nets or they’re just unconnected areas of copper. Once you do that all your vias and through-hole pads should automatically connect with the inner layer copper zones.

The corollary to this is you don’t need vias to connect a through-hole pad to an inner copper zone if the hole passes through the copper zone. This will happen automatically.

Another possibility is that you haven’t filled the zones before running the DRC. Recent versions of KiCad does this automatically more often than it used to, but it’s something to try. Hotkey: “B”

I am quite certain no copper zones have been defined at all yet. In none of the screenshots posted by Juan_Carlos_Cuevas_B I see the tell tale hatched borders of zone boundaries.

@Juan_Carlos_Cuevas_B Do this:

  1. Select one of the inner layers to make it active.
  2. PCB Editor / Place / Add Filled Zone, and use it to draw a polygon around the PCB (No accuracy needed, just draw it outside Edge.Cuts.) I often draw it in the form of a pentagon, because it makes it clear immediately if the zone clipping by Edge.Cuts does not work properly. Something like:
  3. Make sure that you select the right net in the Zone properties dialog.
  4. Close the dialog and press b to refill the zone and calculate internal zone geometry.

Some things about your schematic:

Is the global label VCC the same net as the power symbol VCC? Don’t mix the two. A power symbol already creates a net.

I2C wires, consider using a bus.

Zig zag wires, GND and VCC going sideways or up instead of down and vice versa, symbols not positioned neatly, ugh! Spend time making your schematic neat, it’s you who will have to read it later.