The foot print’s pads manage to appear like that for me.
So what do you suggest?
I’m stumped! Clearly that footprint is unusable. How does it look in the footprint editor? Maybe some soldermask settings have got messed up.
For now I just need a quick fix should I just download the lib from github and replace the file?
You could try that, the github version doesn’t seem to have changed significantly for some time.
What is on the “Local Clearance and Settings” tab for the pad?
Sounds like you may have hit this feature:
The footprint looks ok, but I would try reloading it into the PCB.
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The footprint is indeed defect.
It has clearance settings in the footprint settings enabled.
(-1.8mm)
Fix commited:
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Fix is merged with the library.
@Mike_Lemon
If you use online libs simply update the footprint on your board.
- press e when above the footprint (opens footprint properties dialog)
- press the change footprint button (opens change footprint dialog)
- select
change footprint of 'reference'or change footprint of 'footprint' - press apply
If you use local libs you need to update your libs. (Re run the library wizard to do so.)
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Yes it did it thank you very much!! how did you even find that github topic thing?
I created the pull request i linked because of your report here. (So it was new when i linked it.)
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You said someone managed to fix it in a few minutes? nice! also is there an effective way to update footprints globally in a pcb?
In the change footprint dialog there is a selection for all footprints. This reads all footprints from the lib.
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Only one setting needed fixing. When i saw your post i first checked if the problem is with the footprint or somewhere else.
After finding the footprint is at fault i forked the repo and fixed the footprint in my fork.
Created a new pull request which was merged within a few minutes by one of our library managers. (I’m not allowed to merge my own pull requests)
Another manager found another problem with most of the footprints in this lib. (Wrong naming convention. The “_” before 1EP should be “-”)
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I just remembered that i made a specialized footprint just for this component. (This footprint was already in production. But not in a reflow process. I hand soldered it.)
If you plan on reflow soldering this part you might need to split up the past layer for the exposed pad.
The footprint includes the thermal vias as recommended in the datasheet.
If you plan on using the balancing feature you might want to include them. (The component gets quite hot when balancing.)
TI_bq76PL536.kicad_mod (8.6 KB)
You can also take a look at my github project.
In the ibex project (108s20p battery) i use an stm32 to communicate with 25+24 such chips. There i have 15W resistors for balancing.
In the fennek project (12s1p battery) there are only 2 such chips. (More compact hardware with smaller balancing resistors. Two chips on one pcb.)
Maybe something is useful for you. Yes it is for a large battery.
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Looks complex and I don’t know where to start from when using these designs anyways you say I can’t use the default footprint for my PCB for re flow soldering?
Also do you have a recommended process for automating component assembly?
From what I understand the UI for kicad for that is a pain in the butt and you have you assign each foot print manufacturer link, part number and pos for assembly and that gets very time consuming when you have over 200 component of board…
The paste stencil for the exposed pad will need work.
Normally the paste layer should be broken up into multiple smaller squares.
Example for such an application that gives details on this (yes it is for a qfn package but something similar will apply to your part as well)
http://www.ti.com/lit/an/sloa122/sloa122.pdf
A better more detailed application note (the interesting part is on page 5 and page 6)
It is a good practice to minimize voids within the exposed pad interconnection, so the design of the exposed pad stencil is crucial. The proposed stencil design enables out gassing of the solder paste during reflow and also regulates the finished solder thickness. Typically, the stencil apertures are reduced such that the solder paste coverage is 50% to 70% of the exposed pad area.
And as i said above you will need the thermal vias that are recommentd by TI if you plan to use the balancing feature. (The component gets quite hot.)
It already gets warm just from the internal voltage converters. (At least if you connect 6 cells per chip. Might be less of a problem if it needs to convert from lower supply voltages.)
Make sure you put the part to sleep when you do not need to monitor your battery. Otherwise it uses up a lot of energy. (Even a 60 Ah battery gets discharged within two or three month if you keep the chip active all the time. Yes i learned this the hard way.)
If you do so, don’t connect anything spi related to reg50 voltage supply because this supply gets turned off in sleep mode.
So connect hsel to ldoa (or an external voltage source) for devices connected via the daisy chain. (Yes i learned this the hard way as well. In this years version i could not enter sleep mode because i was unable to wake my parts up afterwards.)
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Aight thanks for the advice but what about automatic assemblies?
I never used automatic assembly. I can not give advice for that. Maybe open a new topic where you specifically ask about that. (Most people simply read the title of a conversation and decide based on that if they can help.)