The paste stencil for the exposed pad will need work.
Normally the paste layer should be broken up into multiple smaller squares.
Example for such an application that gives details on this (yes it is for a qfn package but something similar will apply to your part as well)
A better more detailed application note (the interesting part is on page 5 and page 6)
It is a good practice to minimize voids within the exposed pad interconnection, so the design of the exposed pad stencil is crucial. The proposed stencil design enables out gassing of the solder paste during reflow and also regulates the finished solder thickness. Typically, the stencil apertures are reduced such that the solder paste coverage is 50% to 70% of the exposed pad area.
And as i said above you will need the thermal vias that are recommentd by TI if you plan to use the balancing feature. (The component gets quite hot.)
It already gets warm just from the internal voltage converters. (At least if you connect 6 cells per chip. Might be less of a problem if it needs to convert from lower supply voltages.)
Make sure you put the part to sleep when you do not need to monitor your battery. Otherwise it uses up a lot of energy. (Even a 60 Ah battery gets discharged within two or three month if you keep the chip active all the time. Yes i learned this the hard way.)
If you do so, don't connect anything spi related to reg50 voltage supply because this supply gets turned off in sleep mode.
So connect hsel to ldoa (or an external voltage source) for devices connected via the daisy chain. (Yes i learned this the hard way as well. In this years version i could not enter sleep mode because i was unable to wake my parts up afterwards.)