Thanks again for the response. I guess “boundary” is somewhat of a misnomer when referring to the silk screen. My first thought was that the silk screen would get “cut off” so to speak when printed but it’s really just a clearance for other pads and traces, etc. which make sense.
I will double check the solder mask clearance rules from board house to be sure I got it right.
Ummm . . . . well . . . . I suppose you could use silkscreen objects to define clearances, but the standard KiCAD libraries certainly don’t use them like that. (Electrical clearances, where they might differ from reasonable global rules, are defined for the overall footprint in the footprint’s definition, or on a pad-by-pad basis. Mechanical clearances are generally addressed in the “Courtyard” layers. The FAQ article at What is the meaning of the layers in pcb_new . . . may be helpful.)
As for “cutting off” silkscreen, the KiCAD “Plot” menu includes an option to “Subtract soldermask from silkscreen”. This is a lazy and sloppy (in my opinion) way to keep silkscreen ink away from exposed copper. Some board fabricators will automatically do this to your Gerber files as part of their “service”, since placing silkscreen ink on exposed copper is generally either an error or an oversight on the designer’s part. Personally, I don’t mind a fabricator telling me “Hey! It looks like you may have screwed up. Did you REALLY mean to do this?”, but I get a bit upset when they “correct” things without even telling me about it.
Dale
I think you might have misunderstood what @cabala meant. I think the worry was that the thin line around the pads would result in silk being influenced. Not that silk is used to show a clearance.
Sorry for the confusion I am not being clear with my pronouns. I understand the silk screen is not used as a clearance item or boundary, etc. When I said, “…it’s really just a clearance…” I was referring to the clearance graphics we discussed above.
I just realized the footprint I showed above doesn’t have a courtyard defined so I will do that but yeah my main worry was just that there would be silk screen missing where that clearance is shown but if I understand correctly it is simply a clearance for other pads and traces.
Just note that depending on the manufacturer and their processes the silk screen may have the worst tolerances (compared to copper, drills, mask). The offset of the whole layer may easily be larger than 0.2mm, so with tight silkscreen outlines you risk having them on pads and under components.
That statement is true. However, my unsubstantiated impression is that the industry is moving toward uniform, simplified, tolerances for all features on any layer of a board. Life is easier when my superannuated brain doesn’t have to remember quite so many different things at once.
Dale
I think if silk screen is printed using screen then precision is worse then other layers, if it is printed by printer then precision can be the same. The question is how many % of PCB manufacturers (specially those smallers) uses printers to print silk screen layer.
Just a follow-up question or two.
I am a little confused on what sets the pad clearances. In the footprint editor under pad properties -> local clearance and settings there is a field specifically labeled “pad clearance” and is pretty clear. In pcbnew there is only “clearance” under the net class definition and it seems to be global and apply to track to track spacing and track to pad spacing.
Am I understanding this correctly? Is there a way to have different clearances for track to track vs track to pad/hole in the same net class or is that unnecessary?
The different places to set the clearance come in priority levels. global is the lowest then comes footprint and then pad. Setting any of them to 0 means take the one of the next lower priority.
Regarding clearances, KiCAD does not differentiate between trace-to-trace, trace-to-pad, or pad-to-pad spacing.
(I started to write, “It’s all copper, and clearances between any two pieces of copper is all the same to KiCAD.” But that isn’t true - the copper contained in a fill-zone has its own clearance parameter, which can be set on a zone-by-zone basis and may be different from the clearance parameter for pads and traces in a net class.)
Is it reasonable to apply the same clearance parameter to pads and traces? Currently, I can’t cite a single instance where it causes problems. In the “Good old days” (formerly known as “These trying times”) - 2 or 3 decades ago - it seemed like board fabricators imposed different requirements on every situation: pads, traces, and zones had differing clearance requirements; traces and annular rings had different minimum widths; copper, soldermask, and silkscreen each had their own set of width and clearance parameters. As I noted in my previous post, many of these distinctions have disappeared. With many fabricators it seems like clearances are simply clearances, and widths are simply widths, regardless of whether they involve pads, traces, zones, soldermask, or silksreen.
Dale
Actually what you started to write was true in some way, because the clearance value is applied to all copper without distinction. Usually there are two clearance values in action (all possible pairs of zone, pads, trace, and each zone, pad and trace has its own value) and the higher one is applied. One item (zone, pad, trace) doesn’t have different clearance values for zones, pads and traces.
trace-to-via, pad-to-via, via-to-via,… 
I have no global overview, but based on one PCB manufacturer I think that if that width/clearance is in range about 8 mils than it may be one for all, but if it is smaller then probably not for all. The PCB manufacturer I use has 4mils track width, 4mils clearance, but annual ring is 6 mils. I think photo technology can reach even 1 mils (as all traces and clearances are at the same film) but hole makeing will always be worse precision.
Annual Annular ring is not checked by kicad at this point in time.
Does “annual ring” mean it’s checked only once a year?
I just writen from my fonetic memory. I don’t know that word and its precision meaning
No biggie. We got what you meant, and hopefully most of us here recognize that English isn’t your mother tongue. (And for those of us who it is, still have to rely on spell checkers. For example, I misspelled “tongue” in that last sentence and relied on the spell checker to highlight it for me.) I hope you don’t take offence that I chuckled seeing that you phonetically spelled “phonetic” as “fonetic”. The annoying thing about English is that there are always several exceptions to all the spelling rules because the language grew up stealing words from other languages that have their own incompatible spelling rules.
I used to work at a restaurant where our pantry chef was a very nice woman from Puerto Rico who was raised speaking and writing Spanish. She also spelled phonetically and (I hope) took our constructive corrections in good humor.
Back on topic, one of the things that I wanted to dip my toes into for learning more python and the KiCad API was to create a plugin that would do further DRC checks, and even compare a board file against a design file for each manufacturer. One of the things on my checklist for this would have been checking the annular ring on all THT pads. Sadly, all my other hobby projects are getting in the way of me getting past the idea stage. (I’m pretty sure I mentioned this idea on the DRC survey.) But, I think I recall seeing that someone else has a plugin that does check annular rings. I forget who’s plugin though…
It would be good if forum system contain speller checker. When I write here I have about 80% of words underlined with red wave and don’t know what that means. I just don’t look at it.
To use a speller checker I switch thunderbird to English write there, and then copy, but I do it only in special ocasions as just have no time to play.
I think it is not needed.
It is less work to think while defining vias and pads then to collect the rules from PCB manufacturer in electronic form ready for any kind of software to check.
I have no experience with KiCad, but with Protel most errors as I remember DRC found was that I set rules for checking wrong. During PCB design I changed rules continuously just because it was easier to work.
For example when I start a track it had width equal to track maximum setting. So most time I had this settings set to 10mils jast to not need to change width of any track I am starting. Then when I run DRC it reported me a lot of errors - track too width - I just had to change settings and run it againg to see 0 errors.
I also mainly worked with clearance set to 10 and if forgot to change it to 8 (or sometimes 7) before running DRC I got errors for 0.5mm rasters.
The most important DRC errors are those telling: there is a connection line you overlooked.
This is the responsibility of your browser not the forum software. In fact every modern browser has an inbuilt spellchecker or can interface with spell checkers.
And there is https://languagetool.org/ that can be used directly on their website or even installed as an addon to browsers. (It is available for firefox and chrome)
My guess is that is your browser letting you know that these English words aren’t found in the spell-check dictionary for your language. I can only imagine that it is annoying.
I don’t know if I agree. If designing a board with high density, being able to see in a simple report who of many manufactures can reliably fabricate the annular rings of the various footprints footprints used (and possibly designed and vetted in the past) would make quoting several manufacturers easier. Or even warn the designer that the previously vetted footprint (against the device datasheet and/or physical sample) that they used has annular rings too small for the chosen vendor so the designer can redesign the footprint before getting a board back from the vendor with trace to THT pad or via connections broken because of drill placement tolerance. Much easier to run a quick plugin to warn about annular rings too small than having to manually check the annular rings of all THT footprints and vias used. Especially since in order to calculate annular ring in KiCad currently one has to do the equation (pad size - hole size)/2 on each unique pad and hole combination.
This might be a bit too simplistic of an approach. You need to not only parse separate pads. You need to parse combined pads to get the true result for things like thermal vias or other applications where pads are overlapping.