Footprint Creation Guidelines

Hi I am looking for any guideline in creating footprints. I would like to know about important layers and also about when to use the Fab, CrtYd, Dwgs.User layers. Thanks.

Here is Kicad library convention
It is good for making things look pretty but for the real world applications it is just a waste of time. Most of all that foofaraw just clusters the view in the busy layout for no particular benefit and not really applicable when components a getting smaller.

I suppose there are people who like attention to detail and those who don’t.

KLC has moved to


Good to hear that @ArtG , thank you. And here is the URL to the newest version of this convention
I am also interested in know the minimum required layers for manufactures.

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Define manufacturer? Fab layer was a PITA but I did a through hole board for someone on the west coast and it sure came in handy for him. :wink:

Yeah @bobc, you understand my point. The KLC is especially good when adjusting footprints found on internet or when they are converted from other tools.

I suppose. There are also those who like attention to common sense

@hermit by manufacturer I mean the guys who will produce and/or assemble the PCBs. Why Fab layer was an issue?

Those are two very different “guys” PCB manufacturer doesn’t really care that much what layers you provide. They will manufacture whatever you provide. If you provide just a single copper layer they will manufacture a board with bare copper on a single layer (don’t ask me how I know) So that’s as minimal as it gets. So there is really no “required” layers, it’s what you want to have on your board. Normally, you would provide top and bottom copper (or however many layers you have, top and bottom masks, top and bottom silkscreens (if you need them) and plated and non-plated drill and routing files

As for the assembly house, they don’t need your “layers” at all. Normally they would need your footprint position file, component orientation drawing (can be generated from the silkscreen with various combination of footprints copper, paste etc. to improve visibility) and your BOM.

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There was some lengthy discussion about that question a year or two ago. The conclusion was that many of us had created our own practices for using the “technical layers”.

“CrtYd” (courtyard) is intended to help the board designer arrange components on the board. The lines on this layer show the maximum physical extent of the actual component, plus a clearance allowance for automated component placement machinery, and possibly clearance around large components to mitigate their “thermal shadowing” effects in some reflow ovens. (Hey, even with manual placement you need a few dozen mils between parts to get your tweezer tips between them.) The intention is that the courtyard lines of adjacent components may touch, but not overlap.

“Fab” (Fabrication) is an ambiguous name - I probably would call it something like “Assy”. In KLC, it’s used to show actual component outlines, polarity marks, values, etc. It’s intended to show the assembler which components are mounted at various locations on the board, and how they are oriented. It may also be used for assembly notes, to generate illustrations for, e.g., test procedure documents, troubleshooting guides, maintenance manuals, etc. Prior to the most recent KLC I had already started using ECO1 for this purpose.

“Dwgs.User” (User Drawings) is the layer I use for communication with the PWB etch-and-drill company. On it I place dimensions for the physical outline, plus any cutouts or special mechanical details. I also place all the details regarding construction of the bare board - thickness, layer stackup, copper weight, soldermask color, etc. In the “good old days” (formerly known as “these trying times”, before they got a different marketing company) the board fabricators used a drawing like this as a basis for quoting a job. Receiving Inspection used this drawing to make sure we got what we ordered. Mechanical Design used this drawing to make paper cutouts for planning (or confirming) enclosure design, front panel layout, etc. Now we pass most of this information by clicky-clicky with a computer mouse . . . . and a week later try to remember whether we ordered 1 oz or 2 oz copper; whether it was the second prototype or the third that switched to red soldermask; whether the SMT version was built on a high-temperature substrate or not; etc.

Here’s a sample “Dwg.User” from a very simple board I knocked out last week:



Is it really so? Isn’t it rather like clearance? Thinking logically, if I need 1mm courtyard around each of two components, I don’t need 2mm between them, just 1mm. I would think that a courtyard and a Fab outline shouldn’t overlap.

In any case, if properly drawn the courtyards are a good quick guide but can sometimes overlap or even be neglected case by case basis.

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@dchisholm I really appreciate your answer. I was looking for this kind of tough. Thank you very much for the details.

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You may be right. I have been quite frugal when creating courtyards, so the increased separation hasn’t been a problem. I see that the courtyard allowances recommended by KLC are larger than what I’ve generally used. In practice, the courtyard clearance would be adjusted for the particular pick-and-place or auto-insert equipment used to assemble the board.


Yep. Very much so. I realize that EE’s don’t have an advantage of studying tolerances and clearances taught in mechanical engineering courses but in simple terms, let’s say your pick and place machine have place tolerance of 1mm (which is actually terrible accuracy, but I’m going with your example) That means ± 1mm. So for two identical parts placed side by side, one can have an error in placement 1mm to the right and the other 1mm to the left, thus requiring 2mm of additional clearance between them.

We must’ve had very different “practice” How do you envision adjusting courtyard clearances at the assembly stage? I don’t even know what that means exactly

Obviously, the courtyard clearance is NOT adjusted at assembly stage. The courtyard is one concept used to define a footprint, so the courtyard clearance is adjusted when the footprint is drafted. Of the commercial organizations where I have worked which use CAD/CAE tools comparable to KiCAD, every one has created and maintained custom footprint libraries. The Manufacturing Engineering function (it goes by different names in different organizations) has always participated in the review and approval of footprints admitted to the PCB layout libraries.

While I have never been formally assigned to a Manufacturing Engineering function, I have been explicitly involved with reviews of CAD/CAE library footprints approximately half a dozen times. Component-to-component clearances - i.e., the courtyard dimensions - were a significant concern of Manufacturing Engineering during those reviews. For at least one of my former employers the courtyard sizes were changed based on which assembly line would be used to manufacture the PCB assembly. When new pick-and-place equipment was purchased there was extensive discussion regarding the time and cost of editing existing libraries to exploit the capabilities of the new equipment.


That’s definitely not a trivial problem. In organizations where I’ve seen the problem recognized, the solution has been an administrative process such as “Approved Vendors Lists”. In reality, that only moves the problem one step away from the design engineer, since the Approved Vendors must be actively monitored as they change equipment, use different subcontractors, etc.


We are going through all our footprints to follow the new KLC, and I’m having trouble understanding what the “F5.3 Courtyard layer requirements” section of the KLC means. We’d like to make our footprints as compliant as possible, while still meeting our production requirements.

From the text of the KLC, it seems that the courtyard layer should be 0.25mm larger on all sides than the physical component, with the exception of can caps, BGA, crystals, etc. However, the PNG image below the section shows courtyards that seem to violate the policy. For example, the can cap is much greater than 0.5mm on two sides, and appears to be less than that on the other two sides (though we can’t be sure).

Is the image just not representative the policy? Or is the “Unless otherwise specified…” clause of rule #4 to be applied liberally?


While I can’t speak for the KLC itself I assume the intent is to be IPC-7351 compliant. The following are excerpts from IPC-7351.

Courtyard – The smallest rectangular area that provides a
minimum electrical and mechanical clearance (courtyard
excess) around the combined component body and land
pattern boundaries.

Courtyard Excess – The area between the rectangle circumscribing
the land pattern and the component, and the
outer boundary of the courtyard. The courtyard excess may
be different in the x- and y-direction.

The courtyard excess is added to the maximum dimension that the land pattern or component occupies. The courtyard excess number is added to each side of the dimension in question. It is intended that this addition provides sufficient room for electrical and physical clearance between components and/or land patterns.

The following is a summary of data taken from a series of tables for various package/lead types. Each group also has varying round up factors:

  • Flat Ribbon L and Gull-Wing Leads
  • J Leads
  • Rectangular or Square-End Components (Capacitors and Resistors) Equal to or Larger than 1608 (0603)
  • Cylindrical End Cap Terminations (MELF)
  • Bottom Only Terminations
  • Leadless Chip Carrier with Castellated Terminations
  • Flat, No Lead
  • Inward Flat Ribbon L and Gull-Wing Leads (Tantalum Capacitors)
  • Flat Lug Leads
  • Flat, No Lead
  • Small Outline (SO), No-Lead

Courtyard excess:
Minimum (Least) Density Level C - 0.1 mm
Median (Nominal) Density Level B - 0.25 mm
Maximum (Most) Density Level A - 0.5 mm

  • Rectangular or Square-End Components (Capacitors and Resistors) Smaller than 1608 (0603)

Courtyard excess:
Minimum (Least) Density Level C - 0.1 mm
Median (Nominal) Density Level B - 0.15 mm
Maximum (Most) Density Level A - 0.2 mm

Courtyard Determination The courtyard of any
land pattern is the smallest area that provides a minimum
electrical and mechanical clearance of both the component
maximum boundary extremities and/or the land pattern
maximum boundary extremities. The intent of the courtyard
is to aid the designer in determining the minimum
area occupied by the combination of component and land

Hope this helps.


I don’t know if I missed it the first time around, or if it has changed, but I see that I need to go back to school and get retrained on this!

I have always thought that the courtyard was concerned with mechanical clearances. I thought the electrical clearance around the land pattern (i.e., pads) was addressed by the copper-to-copper spacing requirements. And . . . the courtyard must be rectangular. Following the contour of physical package isn’t allowed.

Just off the top of my head, these requirements have a major impact on power packages, where there is a piece of copper connected to the power tab. The circumscribing rectangle must enclose the heat spreader (plus electrical clearance around it), which means the power package occupies a rather significant piece of real estate. No more tucking a resistor or two into the little rectangle above the component body but outside the heat spreader.


@1.21Gigawatts has the correct answer. We will need to clarify this in the KLC.
(The courtyard clearance is relative to the body or pads, whatever is larger in that particular direction.)

I think newer IPC allows for closer hugging of the component with shapes different than a simple rectangle.
See page 7 of

So i think something like this would be ok.

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