Footprint Creation Guidelines


#21

@1.21Gigawatts has the correct answer. We will need to clarify this in the KLC.
(The courtyard clearance is relative to the body or pads, whatever is larger in that particular direction.)


I think newer IPC allows for closer hugging of the component with shapes different than a simple rectangle.
See page 7 of http://www.ipc.org/committee/drafts/1-13_d_7251WD1.pdf

So i think something like this would be ok.


#22

Yes, you are correct. IPC-7351C introduced contoured courtyards. IPC-7251 also allows contoured courtyards for through-hole components.

Replace the word “rectangular” above with “polygon”.

Sorry for any confusion that might have caused.

Neither standard elaborates on the electrical aspect of this clearance but my interpretation is that it refers to the clearance between the bodies of two adjacent components that may be conductive, or become conductive with contamination, as well as the clearance between the body of one component and the land pattern of another.

The copper-to-copper clearance requirements are usually selected according to manufacturing limitations but in practice the clearance between tracks and lands (pads) is usually greater in order to ensure the track is covered by solder mask.

Just my interpretation, yours may vary.


#23

No confusion. Just wanted to make sure i have read that stuff correctly. (Also i don’t really have “legal” access to these standards. So i am not always sure i can trust my sources.)


#24

@Dan_Green: Thanks for bringing this to our attention.
@1.21Gigawatts and @dchisholm: Thanks for all your clarifications.

I opened a pull request against the kicad webside that will hopefully clarify this rule.


#25

Perhaps it should also be stated somewhere which density level the KLC and Kicad libraries are developed for? I assume it’s the Nominal or Density Level B.


#26

For the courtyard offset, we are inspired by IPC nominal/level B.
The problem is that IPC is a closed standard and we librarians don’t have access to it. (I myself heavily use an illegally published version from a russian server. This is where i got the values for the new resistor, capacitor, … footprints.)


#27

What happens is that the new assembler won’t be able to assemble the board. It is not any different for mechanical manufacturing. Not every manufacturing facilities can hold required tolerances. However that doesn’t affect the definition of tolerances. All you need to do is to find a facility that can manufacture to tolerances specified or redesign the product with looser tolerances.


#28

Thanks for helping clarify this!


#29

We are updating the resistors in our library to fit the KLC standards.

In section S6.1 - Component Reference Designator (RefDes), the KLC references RN as the correct RefDes for Resistor Networks. However, the KiCad footprint library refers to them as Arrays (Ex. R_Array_SIP6)

Can anyone offer insight or clarification?
Which should I use, R_Network/RN or R_Array/RA
Thanks.


#30

Wow a lot of good info here on this thread.

My first KiCad PCB design is nearing completion and I just put ground plane pours top and bottom and the DRC is reporting a number of courtyard errors. First time I have ever seen this error and indeed courtyard.

If I have it correct I could ignore any courtyard error if I believe the board can be fabricated? In my case it will be by hand placement so things like will the tweezers allow me to place components without displacing others for example?

I suspect that part of my errors reported may emanate from a couple of components that I have created. I have not on review drawn some of the border layer detail that I am seeing the main library. I was excited that got to finally create a footprint that allowed me to continue with the design. I may have to go back and edit the footprint once I understand fully what needs to be incorporated in the footprint design.

Appreciate any guidance in that respect.