Hello, I am very new to KiCad. Have finished a sch and traced everything on board. When I use fill zones I get errors. I wanted to ask am I supposed to use Filled Copper zones in both layers?
The erros I get are like
Thermal relief connection to zone incomplete (layer F.Cu zone min spoke count 2; actual 1)
I don’t really understand the nature of the problem. Seems that making the values smaller fix the problem but would the PCB work?
I also see at the getting started that it filling zone is used just on the B.Cu. Are there any resources for learning about all this?
Yes it will work.
It is warning as typically GND zone is connected to GND pads with 4 connections and someone may don’t like if there is only one connection so he would like to look at this specific place to consider may be changing something to allow zone to get more connections.
Just an hour ago in other thread I was reminding articles I have linked 4 years ago:
There are several ways this can be fixed, and the “best” method depends on your PCB. One option is to draw a track from the offending pad. Another option is to set the zone connection of that pad to “solid”.
Do you know what that error message means? I.e, what a thermal relief is?
Thanks for the replies! Well, honestly I am trying to learn. If I understand well thermals are supposed to help with soldering. The filled zone should have a good connection with them (pads?)
I found some interesting info here other new users might find it useful
A question is, for simple PCB I guess everything can work also without Copper filling right? And also both layers should connect to GND probably? What is confusing is that at the “Getting Started” of KiCAD they say
" In the Copper Zone Properties dialog that appears, select the GND net and make sure that the B.Cu layer is selected"
Why just B.Cu layer? or maybe they mean both?
I am attaching an image with the place that has problem
[Edit] By examining the board and re-reading the first reply by @Piotr I think I start understanding the nature of the problem. Some pads are connected to the GND just through the copper zone and KiCad wants that this connection should be in more than a small trace? Am I correct? This would mean that probably spacing the item less tightly things could improve!
@paulvdh Can I manually make connections from a pad to the copper zone?
That screenshot helps.
In your case, U15, pin 13 (GND) is connected only to two small islands.
In KiCad there can simple be just one active layer.
In your case it does not make much sense to put the copper pour on F.Cu because it generates a lot of islands. It makes much more sense to move your copper zone to B.Cu. And then to further improve the integrity of the GND zone, and with that EMC performance, move all tracks from B.Cu also to F.Cu.
Thanks @paulvdh ! Well, pin 13 is connected to GND on the B.Cu but I guess this is not fixing the problem.
I think it will be hard to move all tracks to F.Cu but will give it a try. I am tempted to ask, how copper zone in just the B.Cu will improve things? But I guess I should start reading books!
They don’t mean both, but in the example they probably have connections at top so GND zone should be at bottom (at least). From what you quote I understand that they ask to ensure that B.Cu is selected, but if also F.Cu is selected or not is simply up to you. You probably don’t know, but in previous KiCad versions zone could have only one layer selected and this text can be as it was then.
Shift track going from U5 pad 7 little up (place mouse at it and hotkey D) and you will see that GND zone (after hotkey B) will get second connection to pad 8 and DRC will have one message less.
My example of GND zones at 2 layer PCB you can see here:
At bottom I have there continuous GND zone (no other tracks). All pieces of GND zone at top are connected to bottom zone with vias.
Not KiCad but PCB designer by specifying that minimum are 2 connections (it is somewhere in Board Setup).
At fragment you show us there are 2 pads that should be connected to GND and zone (at top) don’t help in connecting them. I see you have tracks connecting these GND pads at bottom. Replace these tracks with GND zone. You can just change layer in your zone. If your bottom zone will connect all your GND pads than you don’t need GND zone at top.
In classical single layer PCBs with THT elements all tracks were at bottom. If you wish you can do your PCB with all (most) connections at bottom and GND zone at top.
Additional, not important to you information. For reflow soldering to avoid PCB to bend (specially thinner PCBs) in the oven the amount of copper at both sides should not differ too much. Because of this at 2 layer PCBs I have bottom layer 100% GND (no other tracks there - as you see in my example) and all free space at top I also fill with GND. GND at top also allows me to have direct connections (without going through via) between SMD pads that I want them being connected as short to each other as possible.
Thank you so much! You think it is still better to let the F.Cu without a filled Zone or maybe use smaller thermal relief gap and have it there? I am attaching an image of the whole board
Nowadays (when we have everywhere strong EM fields (imagine how strong field mobile phone have to generate to communicate with station 5km away from it) you should have GND zone practically at each PCB. GND zone works like a kind of shield. The best is to have one side being only this zone. If not possible you should reduce breaks in zone to as small as possible - all tracks at other side and only small tracks to allow crossing tracks.
You can place resistors much closer to each other (practically touching courtyard rectangles) making your PCB 2 times shorter. You need not to write their values at PCB (I think no one does it). People write references somewhere near elements, but I have never done it.
I have never searched forum for anything, but I remember there were some discussions about PCBs designed by beginners. If you can find them you will find there lot of information helping also you.
Thank you both so much for your help. I understand it’s very important to avoid making vias. Wondering is it better to have signals making crazy paths on one layer instead of using a few of them (vias)?
I think I am running out of options here (pic). For instance I have to connect the upper rightmost pad of U1 to the third of U2! Probably I will use some 0ohm resistors to cross unless there are other ways. I guess I should add them anyway to the schematic first
Via’s in themselves are not a problem, but on a dual sided PCB, via’s imply tracks plowing through the GND plane (assuming you have a GND plane on the other side), and that is a problem.
The “crazy paths” are not a problem in themselves. Even the long track from R17 is acceptable. Note that it’s resistance will be dominated by R17 itself, and because that resistor also limits the current, inductive effects are also minimal. The long / crazy tracks can become a problem when everything is packed tightly together and you run out of board space for laying tracks. Another possible problem is increased crosstalk.
Making neat rows of parts is something a lot of people do, but from an electrical point of view it’s a bad practice. For example by moving R17 to put it between C3 and U3, the whole long track can be avoided. Another option is to route the signal between the sift resistors around one of the pins of R17. This makes the signal between the shift registers a bit longer (not a problem, unless clock frequencies get very high (100MHz or so). Those neat rows can help a bit with rework and inspection.
When via’s are used on a dual layer PCB, it’s strongly recommended to keep the tracks though the GND plane as short as possible. Preferably below 5mm.
In PCB design there is never an “optimal” or “perfect” result. It’s always a compromise between various aspects.
The same with R25 and R9.
In this case it is not needed but you should also know that with THT resistors you decide how long they are so if it is needed you can have their pads more far away one from another just to reach the right place at PCB. Resistor legs can be used as a kind of third layer.
