Error in the Netlist generation

[BrunoT]

My schematic have multi GNDs and VCCs separated by a small cummun mode choke. When I generate the Netlist for the PCB all the grounds are on the same net GND et all VCCs are on the same net VCC.

Can someone explain my what’s going wrong?

Reards

BrunoT

[radix]

You probably connected the labels together somewhere. Show us your whole schematic or just look through it yourself. Note that the power symbol GND and a label named GND connect to the same net, if you used the symbol somewhere thinking that it’s connected only locally.

I think that VCC2 being separate from VCC excludes bugs or similar.

[Meterman2026]

It doesn’t even have to be global labels - even ‘local’ labels attached to a line with the same name can cause a headache in PCB layout.I got bit by that on a recent board layout.

[BrunoT]

#radix, I’ve triple checked and there no direct connection between the GND and GND1 labels nor between the VCC and VCC1 labels. With or without the local label the result is the same.

As a new user to that forum, I’m not allowed to upload my schematic file.

[der.ule]

Spend some 20min reading other post and the restriction will be lifted or post a better screenshot.

Try using the “highlight net” tool in Eeschema it may help to visualize better.

[SembazuruCDE]

@BrunoT

I’ve triple checked and there no direct connection between the GND and GND1 labels nor between the VCC and VCC1 labels.

There has to be a place that the two are connected. Maybe you have an accidental trace that overlays a symbol (or more commonly hierarchical sheet) edge somewhere. Using the highlight net tool should help because it colors the entire net a nice, contrasting magenta color. I’m sure if you try to highlight your GND net you will also see the GND1 net highlight in magenta, same with VCC/VCC1.

Or, you’ve found a really odd bug that no one else who has done a similar thing has encountered, but I doubt it.

[Naib]

What is the exact footprint used for the common-mode choke. Since this net-shorting is occurring on VCC -> VCC1 and also GND -> GND1 while VCC2 is still unique (separated via R65 0R), it would imply that maybe,possibly the footprint and/or the symbol-footprint link is responsible.

Can you also show a full view because what you are showing clearly isn’t the source of the problem if it is a netname re-use issue and thus a selective view is not helpful

[BrunoT]

Hi,
As all of you, I tell my self there has to be a place that the two are connected. So with the help of the highlight net tool I get the following on the GND net.

If I replace the labels with a simple wire there no more connection between nets.

So my workaround is to use wire indead of global labels.

As soon I will be allowed, I will upload the archive file of the project.

Regards,

BrunoT

[SembazuruCDE]

@BrunoT

As all of you, I tell my self there has to be a place that the two are connected. So with the help of the highlight net tool I get the following on the GND net.

If I replace the labels with a simple wire there no more connection between nets.

What this tells me is that somewhere else in your schematic you have GND accidentally connected to GND1.

[BrunoT]

Except there is no other GND label in the schematic.
Only GND1, GND2L and GND2U labels.

[BrunoT]

Here is the schmatic in PDF.VF_ISO5852SDW_V1.pdf (264.8 KB)

[radix]

The problem lies in U7, U19. Their hidden power pins are global power connections to VSS and GND. By connecting the hidden pins to VSS1 and GND1 you get this situation.

I suggest making a copy of that symbol and modifying it to use normal power pins.

[paulvdh]

Radix apparently found it before I finished typing this post.

----- 8<-------- 8<-------- 8<-------- 8<-------- 8<-------- 8<—

I would probably approach this with a brute force method:

1. Make a copy of your project.
2. Delete a random page from the project.
3. Check if the proplem persists.
4. If the problem is still there, the problem was not on that page:
5. Delete another page, repeat until you found the page.
6. Put the last deleted page back with**[Ctrl + Z]**, or a fresh copy of the project.
7. Repeat the steps on that page, with deleting labels or IC’s.
8. Once you found the error, then fix it in the original project.

It is possible to define a global net name inside a symbol. This is for example used in the power symbols. If any of your schematic symbols has this, and you connect another wire to that pin, then KiCad merges the nets.

Another way of hunting this error down is to open the schematic in a text editor, and then search for the string “GND” and verify each use with the schematic as shown in KiCad.
In KiCad V5.1.x the schematic symbols are not embedded in the schematic itself, but just referenced from a library, so this method may not be foolproof.

[BrunoT]

Well, hidden power pins with GLOBAL power connections. Learning every day, in almost 15 years of KiCad use, I never experience this kind of situation.

Thanks to all.
Reagrds,
BrunoT

[SembazuruCDE]

@BrunoT

hidden power pins with GLOBAL power connections

Unfortunately, you’ve run across a legacy issue. This is how power pins used to be done in the supplied libraries, but it was decided that (for exactly the reason you’ve discovered) hidden power pins on regular symbols is a Bad Idea™. (But it is the mechanism that allows the power symbols to work.) But not all the libraries have gotten updated by the volunteers who maintain the supplied libraries, so it seems that you’ve stumbled across one.