Error in netlist - can't work out why!

I have discovered an issue with a KiCad project I am working on that I only noticed when I started the PCB layout phase. In the PCB editor I have a footprint that has appeared as:

Pins 8 and 9 are showing the same signal name (FIN0) when they should be a pair (RIN0 and FIN0) as per the other three pairs (pins 2 to 7).

On the face of it the schematics look to be OK so I have tried exporting the netlist from the schematic editor. It agrees with the PCB editor:

(net (code 26) (name /Fader_Block/FIN0)
  (node (ref U5) (pin 8))
  (node (ref U5) (pin 9))
  (node (ref U3) (pin 21))
  (node (ref U3) (pin 22)))
(net (code 27) (name /Fader_Block/FIN1)
  (node (ref U5) (pin 6))
  (node (ref U3) (pin 24)))
(net (code 28) (name /Fader_Block/RIN1)
  (node (ref U3) (pin 23))
  (node (ref U5) (pin 7)))

I haven’t been able to make sense of the contents of the .sch files to see where the issue has come from so I am hoping one of the experts can guide me.


The same device as viewed in the schematics (couldn’t post multiple images in the first post).


What happens if you highlight any of the nets in eeschema?

If I click on any of the four affected pads in the PCB editor then it highlights the correct pin in eeschema.

Is there a way to do the reverse process and highlight a net in eeschema and it show in the PCB editor?


There is a proper highlight tool in both eeschema and pcbnew. Explained in section Check Connections with the Highlight tool of Tutorial: Introduction to PCB design with KiCad version 5.1 (Getting Started) (same tool exists in pcbnew if you activate highlight mode in pcbnew and highlight something in eeschema then it also highlights in pcbnew and the other way round works as well)

Here is a bit more of the schematics…

If I select RIN0 then both the RIN0 and FIN0 signals are highlighted in the schematics but nothing is highlighted in the PCB editor. It is almost as though eeschema thinks there is a connection between the two.

The snippet of schematic in my second post (the SN74LS245) is what is inside the hierarchical sheet shown here.


Look carefully at the sheet on top right.
RIN0 and FIN0 are short circuited. See the pink wire ontop of the sheet edge. It would become green when the highlight tool is deselected.


Well spotted! I have no idea how that got there. Time to visit the opticians again to get my eyes tested! :grinning:


Not really. It is not the first time this error arises and I knew where to watch…

FYI in V6 we will automatically create junctions here to make it more obvious:

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