DRC workaround for high voltage clearance

You may be being a bit optimistic here, is 500V your peak working voltage? If so these capacitors are not suitable, good practice puts maximum applied voltage <70% rated voltage and preferably <60% so your capacitors should be 750V or 1000V rated and therefore will be bigger.

The clearances quoted by IPC and others are more safety related than functional and are there for a reason and should be followed even if your design is for purely your own use

No, my peak working voltage is less than that, closer to 300V. I’m just using it to point out that 0805 @ 500V exists. To be clear, I am following IPC, and exceeding it, for traces and fills.

But if the spacing between pads is less than your spacing for traces then it is worse because now you have exposed copper (only air as the insulator) close together at high voltage. I admit that I don’t have much experience with these voltages (only a few HV power supplies for PMTs, spark gap hodoscopes, and NM64 neutron monitors), but the logic of not breaking trace spacing with pads and/or pin spacing seems valid. Yes, I know air is a fairly decent insulator and is one of the few self-healing insulators, but allowing an arc to form across the surface of a PCB can cause carbon trails that will then act like resistors bridging the insulation gap.

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Sure, I understand there is a conflict between pad spacing on components and IPC recommendations. I tend to believe the manufacturers though when they make a rating. Also, I’m hoping to use more generous spacing than IPC calls for, so even if the pads are compliant, I’d rather go bigger.

For what it is worth, IPC spacing can be conservative if you use quality materials and clean processes. Much depends on the environment in which the PCB is expected to run. But, it is a good practice to follow it if you can. Fewer hard questions to answer during a design review.

I am very much looking forward to seeing rule-based DRC implemented. It is a must-have feature for me to consider Kicad for my job.


That the capacitor itself is able to withstand 500V, (Which is the only rating that kemet is concerned about) does not mean that clearances for that part are adequate for using it for such voltages. Those norms for clearances a sum of a lot of different things such as adequate isolation for high humidity or certain levels of contamination of old PCB’s.

Cemet’s rating alone may be adequate if the part gets fully potted, or with conformal coating etc, but the voltage rating Cemet gives for it’s parts are for the pars alone and not for meting any sort of norm. Have you ever looked closely at those X2 rated capacitors with so many stamps from different normalization institutes on them that it’s difficult to find the value of the thing?

For a safe design you always have to use the biggest clearance of your conflicting norms as a minimum. In this case it means that your 0805 part does not meet your clearance and is therefore not fit for your application.

Just had a peek at: https://content.kemet.com/datasheets/KEM_C1009_C0G_HV_SMD.pdf If you believe that PDF, they’ve also got 0603 with a voltage rating of 1000V. Good for them, but not on my PCB.


That part isn’t suitable for assembly and operating > 300V. The pad to pad distance is 0.75mm and the IPC recommends 0.8mm for uncoated @ sealevel assembly.

The KiCAD pads for 0805 aligns with the IPC and also Kemets recommended distances of 0.9mm separation, which itself is good for 300-500V assembled uncoated.

Thus your specific problem is either in your component selection or aspects of how you setup the constraints.

Now 5.1.x doesn’t have too sophisticated keepout rules (I am hoping v6 is flexible enough) so what I end up doing right now is lots of keepout shapes,to help me not get too close

Fair enough, it’s probably prudent to use a larger part, but if a component is specified to 500V, saying “it’s not suitable for 300V” seems a little weird. There is definitely a conflict between IPC and manufacturer specifications. (They don’t require potting)

It is not weird, and there is no conflict.

As said before:
Kemet only concerns itself with the strength of the isolation between the capacitor plates.
This is logical, as Kemet has know knowledge of how the part is going to be used.

IPC https://en.wikipedia.org/wiki/IPC_(electronics) concerns itself with guidelines for making reliable products.

On top of that there are norms such as UL and CE, and certifications for that which are yet again on another level.

If you want to build a product and sell it on the mass market you probably have to conform to all of those standards, Not just the one that suits you best. It’s one of those things that makes product design a headache.

Another example are the voltage and current ratings on switches and relays.
If the contacts of a relay are able to switch 230Vac @ 10A, this is no guarantee whatsoever that it meets isolation specs between the switches and the coil.
The (almost) square blue “Songle” relays from China are particularly bad in this aspect, while the Omron G2 (clones?) have a wide isolation distance between coil and contacts, they even have a labyrinth built in to increase creepage distance.

Its not really weird, not only because of what @paulvdh and I have stated but the difference between working and transient

The IPC typically is concerned with working voltage, the voltage that the circuit is expected to stand off for a considerable length of time. When you consider BSEN-60664, the distance before a flashover occurs for a short duration transient is a lot larger. If a circuit is anticipated to experience an overshoot (be it due to an underdamped 2nd order system, supply overshoot or lightning strike), you want to ensure that the dielectric will not break down.

so having this standoff 300V is extreamly questionable, but on a system that operated at say 250V MAX but transient to say 350… sure (NOTE: I wouldn’t dream of putting a 0805 across 300V … even if creep&clearance appears ok, even with parylene conformal coating )

Likewise treating this part as a discussion point, just because it is rated for 500V does not mean you would put it into a system with 500V because it is never good to run a part at 100% rating

I’m using capacitors with a similar rating in a HV project. I don’t think there’s a way around proper cleaning, followed by potting.

I’ve written up a little bit about clearance matrix specification using the new design rules system. It’s not reviewed yet, but should give an idea what working with v6 will look like:

I also started a thread here, which seems to have been missed due to missing keywords ^^

One can specify zones on on a user layer dedicated to conformal coating / underfill / glob top encapsulation (e.g. calling them Encapsulation1, Encapsulation2, …), and then localize clearance rules via

(condition "A.insideArea('Encapsulation*')")

or something similar.

Pretty much this, but even then it is questionable.
If you are dealing with a couple sure you can deal with this. But at a large automated assembler or on a shop floor…
I would question whether parylene would get under the component. This is why I simply don’t take the risk.

As to the new design rules, this is the only thing that has me really excited with regards to V6. I have 4 cards I am just tidying up for release and then I want to fork my repositories and start playing with V6. Presently all 4 are a mish mash of keep out zones or relying on eyeballing and measuring… Not idea but it works.

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Things are being tidied up and some issues found and solved as we speak. It’s the right time to start playing with it, but I wouldn’t rely on it to be 100% water tight yet. A few more weeks and it’s going to be awesome.

There are some interesting open questions when it comes to design rules and creepage, of all things. I’ve brushed up against it trying isolation slots.

I only tried parylene insulation twice, and it was probably way too thin to be relevant.

Underfill should work coming from an automatic dispenser, if you can make the inspection afterwards happen (SAM).

You might also find these interesting - there are quite a few ideas out there that might help solve the problem. Of course, the clearance choke points still need to be consciously permitted (for example by creating modified footprints with encapsulated modified clearance zones), but at least then we’d be out of the uncanny workaround valley.

“A simple version would be to define an area where all constraint are set to
default, better solution is to define acceptable size in this area.”

“It would be nice to have the option of setting a start and end line width
for individual segments in pcbnew. This would be a smooth taper from a
wide, low-impedance trace to a narrower trace. Note, the taper should have
an option for linear or curved.”

“In Kicad 5 all traces have round ends. In some cases it is necessary (or at
least desirable) to have precise square ends that coincide with the
endpoint’s X and Y.”

FWIW I have just checked IEC62368 for creepage and clearance requirements:

Creepage, assuming pollution degree 2 and material group III (typical PCB material) boils down to 1mm per 100V RMS working voltage above 200V

Clearance, 0.2mm for basic or supplementary insulation, 0.4mm for reinforced insulation up to 800V peak working voltage

For those unfamiliar, IEC62368 is the go to standard for safety for most electronics and completely supersedes the now obsolete IEC60950 and IEC60065

As pointed out elsewhere the capacitor alone probably meets the requirements of the standard since creepage on a ceramic surface in a PD 1 environment is reduced to the clearance distance so the limit becomes the dielectric breakdown voltage

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This is a great discussion.

One feature that might be worth thinking about is something to automatically set clearances based on peak voltage and whatever standard one might apply (or just pick one). This has the advantage of simplicity, and not relying on a setting a matrix of clearances for lots of different net classes. Clearance would be specified by relative voltage, as it should be.

For example, Net1 is set to 100V, and Net2 to 200V. The clearance between Net1 and GND is 1mm, the difference between Net2 and GND is 2mm, but the clearance between Net1 and Net2 is 1mm. (This is something I face when using multiple resistors in series over high voltages.)

Just a thought, I’m sure there are problems with it. :slight_smile:

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I recently worked on a B6 bridge board that immediately had to incorporate clearance matrix information, so I should mention two aspects:

  • When using a sparse definition of self-clearance and mutual clearance values per net class, a pretty straight-forward block matrix form emerges, where the diagonal elements are low voltage clearance and the off-diagonal ones are all the same value of high voltage clearance.
  • Since the definition is pretty repetitious and a common case for multi-phase high voltage circuits, a template construct is proposed in https://gitlab.com/kicad/code/kicad/-/issues/5696 . I’m confident that it’ll take most of the lead out of clearance matrix definitions, while not compromising the power of rule scripting.

For example, Net1 is set to 100V, and Net2 to 200V. The clearance between Net1 and GND is 1mm, the difference between Net2 and GND is 2mm

This seems like an intrinsically 1D description for a 2D problem, so some translation is necessary. For simple cases, this seems akin to nesting clearances to avoid clearance specifications towards multiple other net classes. Unfortunately, there’s a catch: clearances aren’t signed, so two resistive dividers from GND to HV would each cause HV to be the innermost net class, and have twice the maximum clearance from itself than from GND.

One could also think of a clearance matrix tool that derives clearance matrix elements from voltage ranges specified for each net class w, with respect to a common reference potential.

With all that work put into the definitions, there might still be some additional information missing: what about voltage transients? Are there some correlated potentials?

Here’s another thought:

At least in power electronics, one can imagine sets of nets that have smaller clearances among each other and are localized in one region of the board, while keeping a substantial distance from any other net in the design. In that sense, grouping net classes and specifying clearances with respect to such a group would be physically plausible while being almost equivalent to a block matrix formulation in the clearance matrix - only that one wouldn’t need to fill in so many fields with mostly redundant clearance values. It is then up for debate whether this is a true case of nesting.

Finally, clearance constraints are not just about the 2D clearance matrix. Localizing clearances to individual layers makes it 3D, and including inter-layer constraints blows that up to 4D. So the general case already is that definitions are sparse in nature, and one should look for ways to better describe the rules in an abstract way. Net class grouping may be an ingredient, but it may be more of a shorthand notation for clearances than a general solution.

Pretty sure this is also for Basic or Supplementary insulation (at least it is in IEC61010), so it applies only where insulation failure would present a safety hazard. The IEC/EN standards rarely say much about Functional insulation - they don’t care whether your dingus works or not, as long as it doesn’t present a safety hazard. The IPC guidelines are more conservative, and more concerned with proper functionality and reliability.


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