DRC workaround for high voltage clearance

You might also find these interesting - there are quite a few ideas out there that might help solve the problem. Of course, the clearance choke points still need to be consciously permitted (for example by creating modified footprints with encapsulated modified clearance zones), but at least then we’d be out of the uncanny workaround valley.

“A simple version would be to define an area where all constraint are set to
default, better solution is to define acceptable size in this area.”

“It would be nice to have the option of setting a start and end line width
for individual segments in pcbnew. This would be a smooth taper from a
wide, low-impedance trace to a narrower trace. Note, the taper should have
an option for linear or curved.”

“In Kicad 5 all traces have round ends. In some cases it is necessary (or at
least desirable) to have precise square ends that coincide with the
endpoint’s X and Y.”