DRC Clearance error isn't real

I have dozens of these violations:


The design rules are all default for 6.0.2. There is no clearance rule anywhere with a 0.5080 mm dimension. Not sure what to do with this. It feels like a bug. All violations are between zones or zones and tracks. In no case is there a clearance that is less than the default settings for the Default rule.

I came across while searching:

Sounds like a variant of what I am seeing.


Doubtful a variant of that bug, that was pretty specific to an early development issue. Are your zones set to different priorities? They need to be if they are very close together, otherwise it doesn’t know which one “overrides” the other.

There is no clearance rule anywhere with a 0.5080 mm dimension.

That’s the default zone fill clearance. Can you attach your zone fill properties too? Or just try bumping the priority settings on them so they’re different.

Well, a DRC check should run a check based on defined rules for the board, no hidden settings that do not necessarily travel with the defined design rules. In other words, I ought to be able to move design rules from board to board and have a full and consistent set of them.

I guess I am saying I disagree with how this works. It doesn’t make sense to me.

I went ahead and changed the zone clearance to 0.2 mm, which is 0.05 mm less than the smallest copper-to-copper gap relevant to these elements.

As you can see below, I still get an error, even though everything is 0.25 mm or more copper-to-copper.

The clearance in that dialog should be a pull-back amount from the edge-inwards. The only thing that should produce DRC errors in this case are copper-to-copper distances that exceed the rules as defined in the board configuration.

If I am correct, if I were to import the board setup into another project, one that happens to have a different zone clearance defined in the zone dialog, the new board will not have a full set of design rules for DRC. I really think this needs to be limited to configuration in Board Setup.

I can deal with this by simply ignoring it. I know the board is fine. This would be dangerous with a denser/more complex board.

Eh you’re just misunderstanding what “design rules” means here. Your design rules are still totally portable. It’s just that objects in the layout have clearances of their own as well. This is just like every other layout software I’ve used — it’s normal. And nothing is hidden, it shows you that dialog when you create the zone.

As you can see below, I still get an error, even though everything is 0.25 mm or more copper-to-copper.

Did you update all the zones? It sounds like you’re thinking this is a global setting, not a per-zone property.

I don’t believe it works like this in Altium. Frankly I have to go back and look because I can’t remember ever running into this kind of a collision of settings in 20+ years of using it. But that’s a different matter.

No, design rules should be like the single canonical specification document that everything is checked against. What’s the use of defining a bunch of rules if they can get screwed-up locally by individual items?

In this specification I am literally saying: “I am OK with copper-to-copper clearance being 0.2 mm anywhere in this design”. And yet, I got DRC errors for clearances that were more than twice that distance.

Yes, of course, I re-poured everything. Not my first PCB design rodeo. And, yes, of course, I know the zone dialog settings are not global.

Ultimately this is what cleared all the errors:

import pcbnew

board = pcbnew.GetBoard()
items = board.AllConnectedItems()

zones = []

for item in items:
	if isinstance(item, pcbnew.ZONE):

for zone in zones:
	zone.SetLocalClearance(int(0.2 * 1e6))

filler = pcbnew.ZONE_FILLER(board)

Ran a DRC after this and all zone and zone-to-track errors are gone. Zone priority level is 0 for all zones, so, in this case, it didn’t matter.

What might be lost in this conversation is that there were no real copper-to-copper violations ever, despite the DRC errors. By “real”, I mean, you have to redo your run of 500 boards because of the error.

Anyhow, no big deal. I fixed it. I do not agree with the way this works, but I can get used to it. If it can be fixed with a little code, I’m happy.

Thanks for pointing out where this “0.508 mm” setting was hiding.

I should add: If someone is drawing overlapping copper pours, well, then things take a different turn. Frankly, I don’t remember ever doing that in 20+ years. I always define them exactly the way they have to be drawn, precisely because software will shaft you if you let it.

Where from the idea that anything should work like in Altium?

They can’t be screwed-up locally. If it is really so - that is a bug.
You have to have in mind that V6 is rather new. It was released only 3 months ago. During 3 years the bugs in V5 were fixed, fixed and fixed ending with V5.1.12 version.
I’m close to be sure that in V5 after refilling the zones you will never get any clearance error regarding zones.

I don’t know Altium, but I used Protel 3 for many years. There before filling zones I always changed clearance setting from 8 mils to 10 mils and then (after filling zones) back to 8 mils to satisfy DRC. Whenever I had to refill any zone I did that ‘procedure’.
It is because I allow tracks to be at short distance 8 mils from other things but I don’t like zones to be so near to everything. In past (previous century) it happened that we got shortages at PCB in such cases.
I like that in KiCad I can set clearance for each zone once and forget about it forever. For example if I have zone at higher voltage (like PoE 48V) I set its clearance higher.

So, not sure but may be you fight with the bug.

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