Pcbnew DRC needs a check for clearance between the silkscreen layer and pads on the associated copper layer. This will pull up errors in footprint design and positioning of component refs.
Silkscreen on a pad can render the pad unsolderable.
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The pcb manufacturers CAM software usually takes care of that and removes Silkscreen from pads.
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These days most plotters can plot both black and white, and as mentioned above, most software at FAB does a pass where they plot a set of Clear PADS over a silkscreen, which auto clears any offending over-pad lines.
Emphasis on “usually”. I’ve had pcbs come back with silkscreen on pads. Doing the check up front is applying the " measure twice - cut once" rule, and can save time and money.
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And when the CAM software clears the silkscreen, you end up with no component Ref on the PCB. Therefore a DRC warning would still be useful
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Is your issue bad part outlines, poorly placed reference texts ?
A simple plot-clear will address any part outline bleed, but I guess if your texts are poorly placed, then some DRC could be useful.
I think there has been talk of making DRC text-vector-aware, as I believe right now DRC uses only the bounding box.
Maybe silk DRC can come when DRC is text-vector-aware ?
The issue is both bad outlines and text. e.g. footprint TO_SOT_Packages_SMD:SOT-323 in the online library has outline all over the pads. I didn’t notice this until I was doing a thorough manual check using a gerber viewer. I’ve no idea how many other library parts have this issue.
If the DRC can only do bounding box checks on text, thats better than nothing - though it would be nice to be able to turn the check on and off.
I prefer not to rely on a pcb supplier to get this right.
A DRC check might be useful. In the meantime, check the “Subtract soldermask from silkscreen” option in the Plot dialog.
To stop the problem at source requires creating new library parts, if the outline goes over the pads.
The policy on silkscreen seems a bit confused - is it to show an outline before placement, after placement, for documentation? Actual implementation seems to be a mix of all 3, which is not great. I found some Eagle parts where there is an outline which switches to Drawing layer over the pads, then back silkscreen, which I didn’t like at all.
But I am more and more appreciating the notion that if I want quality footprints, I have to make my own libraries.
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I agree on all of these points. Silkscreen is always a means for one human to communicate information to another human. Unlike copper layers, this communication can accomplish its purpose with few restraints. For many of us, silkscreen is the last task in a design and subject to errors arising from a need to get the job finished quickly. As I put the finishing touches on silkscreen I typically work with other layers not displayed so lettering that lops over onto a pad might escape my final visual inspection.
(On the board I did just a few weeks ago, I forgot to put the drawing name on the board. Not a disastrous error, since the drawing number WAS on the board. But switching the " + " and " - " designations on the battery connection terminal block could lead to a catastrophy!)
No, I don’t expect DRC to catch those two errors but it definitely would be helpful to flag the places where silkscreen lands on top of a pad.
[quote] I prefer not to rely on a pcb supplier to get this right.
[/quote]
In prior incarnations I have received boards with silkscreen placed on top of pads - exactly like my Gerbers told the supplier to do. I don’t know how difficult it would be to implement and code a DRC check for silkscreen violations, but it would be helpful.
Dale
Agreed, there is the ability to check the “Subtract soldermask from silkscreen” option in the Plot dialog.
- that avoids re-spins, but currently users need to visually check if they actually need to move text.
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