Digital simulation D Flip Flop (ngspice in KiCad/Eeschema tutorial)

Maximiliano_Fried · November 28, 2020, 11:35pm

Hello im following the tutorial : http://ngspice.sourceforge.net/ngspice-eeschema.html#digi

I’m trying to make a D Flip Flop. But I’m not having expected results on simulation.
Can you tell me please how i need to configure the CLOCK and DATA pulses and also if i need to insert some parameter to the 74HC00 model?

CIRCUIT:

MODEL (From Tutorial):

*Delays are given for Vcc = 2V/4.5V/6V (HC) from the
*Philips data sheets. http://www.philipslogic.com
* Delays are given for Vcc = 2V/4.5V/6V .
*Used delay:  Td = (Tpd-Tr/2)*(4.5-0.5)/(Vcc-0.5)
*The gate delay has to be set to tpd minus 3ns for the input filter
*and another minus 3ns for Trise/2
*td1 = tpd  - 3ns - 3ns
 .param vcc=5 tripdt=6n
*The 74HCXX gates
*2-input NAND gate
*vcc 2 /4.5/5 /6
   *tpd 25n/9n/7n/7n
 *tr 19n/7n /  /6n
.SUBCKT 74HC00  in1 in2 out  NVCC NVGND  vcc1={vcc} tripdt1={tripdt}
.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)}
.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver
*Cin1 in1 0 3.5p
*Cin2 in2 0 3.5p
abridge2 [in1 in2] [din1 din2] adc_buff
.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0})
a6 [din1 din2] dout nand1
.model nand1 d_nand(rise_delay = {td1} fall_delay = {td1}
+ input_load = 0.5e-12)
abridge1 [dout] [out20] dac1
.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0}
+ input_load = 5.0e-12 t_rise = {tripdt1}
+ t_fall = {tripdt1})
Rout out20 out {Rout}
.ends

RESULTS on comments.

Thank you!

Maximiliano_Fried · November 28, 2020, 11:35pm

RESULTS:

holger · November 29, 2020, 8:29am

What is the result you are expecting from a D flip-flop?

Unfortunately you are repeating a model that can be found elsewhere, but you don’t share your circuit netlist calling this model.

Jairo · November 29, 2020, 1:37pm

Your D-Flip-Flop circuit seems to work fine. Maybe am I wrong?

If you need help with the model, I can try to help you.

Perhaps a better optimized D-Flip-Flop model can be made without so many DACs or ACDs involved. The result will be the same but with less resource consumption. (without much difference).

A greeting

Maximiliano_Fried · November 29, 2020, 2:17pm

thank you Jairo! The idea is to build a shift register as you saw in my other post!

holger · November 29, 2020, 3:02pm

Basically ngspice allows three different paths for analog/digital simulation.

There is the pure analog way: You define gates at transistor level or with controlled voltage sources (B source). Then all signals are analog, even if you put several digital gates together.

On the other side there is a pure digital, event based simulation possible, which is much faster than with analog gates, but is of course lacking any interface to the analog world.

And you may use a combination of both, digital, event-based gates and analog circuits. The link between the two are the DAC and ADC interfaces. These interfaces do not consume many resources. Especially if one considers that D flip-flops are available as digital parts (see ngspice manual 12.4.12, 12.4.16).

I have made a comparison of the three approaches in my talk to FOSDEM2019. See picture attached.

Simulation files are available with the ngspice distribution (ngspice/examples/digital)

You could even consider programming the shift register 4021 as a digital state machine (12.4.18). A binary up/down counter has been created this way (Is binary counter Spice model available?), although the 4021 is more complex.

Jairo · November 29, 2020, 8:20pm

So First, we are going to analyze the 74HC00 model that you have shared with us.

ngspice has an extension called XSPICE that contains components that look more like logical or analog functions than physical components. You can see the list of components in section 12 of the ngspice manual.
ngspice-33-manual

All lines beginning with an asterisk (*) are comments.

.SUBCKT 74HC00 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt}
[…]
.ends

The subcircuit that defines the 74HC00 component has 5 input / output pins (in1 in2 out VNCC and NVGND) and 2 parameter inputs (vcc1 = {vcc} and tripdt1 = {tripdt})
And it closes with the .ends line

abridge2 [in1 in2] [din1 din2] adc_buff

abridge2 is an instance of “adc_buff” model, and has a unique name.

.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0})

This is the analog-to-digital interface. This model is described in section 12.3.2 of the manual.

a6 [din1 din2] dout nand1

This is similar than abridge2. A6 is an unique name and a nand1 instance.

.model nand1 d_nand(rise_delay = {td1} fall_delay = {td1}
+ input_load = 0.5e-12)

This is the model of a nand gate. The plus (’+’) symbol indicates that this line belongs to the previous one.

abridge1 [dout] [out20] dac1
.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0}
+ input_load = 5.0e-12 t_rise = {tripdt1}
+ t_fall = {tripdt1})

Another instance with its corresponding model.

Rout out20 out {Rout}

And ends with a resistor

So you’ve basically built a D-Flip-Flop from Nand gates with individuall ADC and DAC interfaces. But, hey, there is already a model D flip-flop in the XSPICE components. (section 12.4.12).

Let me know if you have any questions.

Ste · November 30, 2020, 4:36am

The circuit shown in this thread is for a D-type Latch, not a D-type Flip-Flop. I believe @Maximiliano_Fried is trying to create a 74HC74 which is indeed a Flip-Flop. I’m not sure it matters for the final application circuit, but pointing it out just in case.

@Maximiliano_Fried, I highly suggest exploring the Section 12.4.12 option described above. If you study @Jairo’s analysis above, you can probably use similar techniques to figure out how to make your own subcircuit using a d_dff XSPICE device.