Different net clearance for other nets (signals) and board edge

Is it possible to have different net class clearance for other networks and for board edge?
I have high-current power network, which I prefer to have rather large (1mm) clearance to other nets and signals, but it doesn’t have problems to be near the board edge. Even more, some power connectors have their pads closer to the edge than this clearance!
Is it possible to have different clearance for different obstacles?
Maybe, some hacks for board edge?
As I need proper board edges for fabrication, expanding board doesn’t look like robust solution!

In my opinion specifying clearance for something and not from something to something is now the biggest lack of KiCad.

Those discussions and reported issues may be related (if yes, it still as feature request)




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See also https://gitlab.com/kicad/code/kicad/-/wikis/KiCad-6.0-Roadmap#constraint-management-system.

@blacklion, most of those feature depend of the new file format that the developers start to test this week to store the parameters needed. https://gitlab.com/kicad/code/kicad/-/merge_requests/135
If you want to help (to shape) this feature, read, comment and propose specific behavior at the gitlab above links.
After developed, this feature will be only in nightly versions until v6 release.

So, PCB feature depends on EE Schema file format, do I understand this right?

The above is my understanding of the development cycle.

It depends for files change that are planed in both (Eeschema and Pcbnew) to store the matrix-clearance information. Despite it’s is essentially correlated with Pcbnew (not Eeschema), it is planned some better integration of the design rules between Eeschema-Pcbnew. And also the developers team started by the Eeschema file.

For now is just possible to achieve a general clearance value using the Net-class at Board setup.

In my example, I created Power and assigned it to +12V, … other power signals.

See that is demanded a 2mm clearance for this kind of track class.

But, it stays not allowed some different value for board edge, as you asked. This will be the feature (dependent of the file format).
I already designed some board as you wish. The approach was change the class configurations as I was doing the work and, at the end, ignore some DCR warnings/errors.

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