Define different annular width for vias vs PTH

[SKSSF]

I frequently buy my PCBs from Advanced Circuits, and they have different annular width requirements for vias vs component PTH. I only see a single annular width spec in Board Setup | Design Rules | Constraints–is there a way to specify annular widths separately for vias and PTHs? Or should I submit a feature request? Thanks!

[teletypeguy]

What concerns do you have about PTH sizes? I only have PT holes as part of a footprint, and they are sized for the component; annular ring is usually only a consideration for pretty small pitch (eg: throughole usb-c…). But all of those footprints are simply reused and not something that I need to change.

For vias, I generally use 0.6mm dia and 0.3mm hole (for 0.15mm annular ring). This is a no-extra-charge size for most board houses. Sometimes I go down to 0.5mm dia with 0.2mm hole (also 0.15 ar) – even that size does not seem to be extra-cost. I generally use jlcpcb or pcbway. I used advanced pcb many years ago, but then found that I could pay about 1/10th the cost, even with dhl, and generally get a couple of weeks to door. I also use jlcpcb for pcb plus assembly (even just partial), which has been awesome and pretty cheap.

[SKSSF]

Advanced circuits permits 0.005" (0.127mm) annular width for vias and 0.007" (0.1778mm) for PTH. I too am using 0.3mm/0.6mm vias, which passes DRC if I set the annular width min to 5mils, but fails for 7mils.

So…I have to run DRC twice:

1. With annular width set to 5mils to make sure everything is within spec.
2. With annular width set to 7mils, during which I must ignore all vias that don’t meet spec.

I’ve submitted a feature request to gitlab. Not a major PITA, but this would be nice for more complicated boards.

[jmk]

As @teletypeguy comments: copper for component PT Holes is set with pad size and shape and hole diameter. That has nothing to do with annular rings for vias.

[hmk]

I must admit that I don’t have enough experience with custom rules to know for sure, but perhaps it would be possible to set up a custom rule for PTH minimum annular width and have the regular minimum annular width set to the lower value for vias?

[RaptorUK]

When you have it figured out please let me know, I have a similar issue . . .

When is a via not a via?

The PCB I’m currently working on (a redesign to address issues) uses a ti MSP430 microcontroller on a ti package (drawing ref: RHA0040B) VQFN (40 pin), 6 mm × 6 mm body and 4.15 x 4.15 thermal pad. The specs for the footprint include thermal vias, with suggested 0.2mm holes. So I initially used the ti VQFN 40 pin footprint that is included with KiCad (Package_DFN_QFN:Texas_RHA0040B_VQFN-40-1EP_6x6mm_P0.5mm_EP4.15x4.15mm_ThermalVias ) but ended up modifying my own to match what was suggeste…

[mf_ibfeew]

For all advanced requirements the custom rules should be used. This is a very mighty feature, which sadly needs a bit effort to learn it.

I would recommend to study the pcb editor dcumentation, it contains a large chapter about the custom rules. The custom rules dialog itself shows a short introduction into the syntax, and the FAQ section in this forum includes a thread with custom rules examples.

(version 1)
(rule "annular_via"
   (constraint annular_width (min 0.05mm))
   (condition "A.Type == 'Via'"))

(rule "annular_pad"
   (constraint annular_width (min 0.2mm))
   (condition "A.Type == 'Pad'"))

note: not really tested (I personally try to keep things simple - so I simply use the larger of these values for both: via and PTH holes)

[paulvdh]

I had a look at:

AC%20Capabilities%20June%202022.pdf

and they do indeed list different minimums for different kind of holes. I find this a bit unusual because all holes are made with the same process (unless you start doing something exotic such as laser drilling).

I’m not sure if this is common enough to warrant a modification in the board setup (but I’m also not a KiCad developer) Using custom rules such as Mark Freitag suggested on gitlab is a usable alternative.

[SKSSF]

@mf_ibfeew

For all advanced requirements the custom rules should be used. This is a very mighty feature, which sadly needs a bit effort to learn it.

Thanks for the info–this is powerful.

Can you advise–which takes precedence? The custom rules or the rules from Design Rules | Constraints?

[scandey]

Based on the docs, the constraints are universal absolute minimums, with all other rules (including custom design rules) intended to provide specific restrictions beyond the constraint values.
https://docs.kicad.org/8.0/en/pcbnew/pcbnew.html#configuring_design_rules

If you are curious when constraints or rules are being applied, you can use Inspect > Clearance Resolution to investigate specific objects (or pairs of objects).
https://docs.kicad.org/8.0/en/pcbnew/pcbnew.html#clearance_and_constraint_resolution

[SKSSF]

@scandey

Based on the docs, the constraints are universal absolute minimums, with all other rules (including custom design rules) intended to provide specific restrictions beyond the constraint values.

Thanks for the clarification and tip. If I understand you correctly, I should put the more stringent minimum in the constraints, and then further constrain via custom design rules? THanks!

[scandey]

Yes, generally the “constraints” are the actual manufacturable distances/sizes as defined by the fabrication house you select. Some constraints will not match a manufacturer’s requirement (and vice versa) but in general that’s your starting place.

Then you might have specific requirements (though equal to or larger than the minima from the fab house) on separation or sizing of specific tracks, pads, etc, enumerated with the custom rule system as you’ve seen discussed above.

[mf_ibfeew]

This is not correct, the custom rules always override the generic constraints values. The current hierarchy is:
custom rules → generic constraints → netclass values

In my opinion this was a dangerous decision - now it’s easy to mess up a design with a bad written custom rule which violates the manufacturer minimal values. Additionally the impact of a rule is not visible on one quick glance - so it’s harder to detect mistakes before board production starts.

On gitlab there is a open feature request to introduce definitive minimum values for a board, but it got not much support in 3 years: Design Rules: establish definitive technology constraints (#6030) · Issues · KiCad / KiCad Source Code / kicad · GitLab

[davidsrsb]

@paulvdh

they do indeed list different minimums for different kind of holes. I find this a bit unusual because all holes are made with the same process (unless you start doing something exotic such as laser drilling).

Probably due to a bit for a 0.3mm finished hole being centered better than a 3mm bit. I wonder if the via drilling uses the same machine as those fine bits must need changing frequently

[paulvdh]

Machines for drilling PCB’s regularly have automatic tool changers with magazines for hundreds of drills, and those get replaced automatically after a pre determined amount of drilled holes. All those drills are tungsten carbide with a 3.175mm shaft and collet holders. Runout is negligible Those machines use high quality spindles with 60.000rpm or higher, runout simply is not an option.

To get an idea of how this drilling works these days, see the video below.
Each of the drills has trays with 400 drills.

PCBWay PCB manufacturing machine-Automatic drilling machine