When is a via not a via?

The PCB I’m currently working on (a redesign to address issues) uses a ti MSP430 microcontroller on a ti package (drawing ref: RHA0040B) VQFN (40 pin), 6 mm × 6 mm body and 4.15 x 4.15 thermal pad. The specs for the footprint include thermal vias, with suggested 0.2mm holes.

So I initially used the ti VQFN 40 pin footprint that is included with KiCad (Package_DFN_QFN:Texas_RHA0040B_VQFN-40-1EP_6x6mm_P0.5mm_EP4.15x4.15mm_ThermalVias ) but ended up modifying my own to match what was suggested by ti for the position and number of thermal vias and resultant solder paste layer.

All was good till I came to run my DRC, I’ve set a min hole size of 0.3mm (design rules constraints) to fit the capabilities of JLCPCB (I use them for prototypes) and uvia holes to 0.1mm also as per JLCPCB. All my thermal vias fail DRC as the holes are too small . . .

Now I know it’s not the end of the world, it’s still fine to get fabricated, I can ignore these errors in the DRC and all will be good, but it is a little annoying. It occurs to me that KiCad footprints have thermal “vias” but they are not actually vias but PTH pads. Am I unreasonable thinking that we should be able to place vias in the footprint editor ? I guess I am because I can still do what I need to do to get this PCB over the line with very little extra effort . . . I’ll probably create a feature request anyway . . . :slight_smile:

You set minimum holes to 0.3 and made holes 0.2 so DRC reported it.
If you replace these pads with 0.2mm vias they still will have too small holes.

I understand uvia (never used them) as going to nearest internal layer. Do when you have only 2 layers and nearest is the opposite layer all vias are uvias? I don’t think so.

A couple of thoughts <but actually a comment to the creators of the suggested footprints/land patterns of datasheets>:

  • 16 thermal vias in a 4x4mm area to relief the heat of a MSP430?
  • Is such a small hole of 0.2mm necessary, in some cases pushing manufacturing capacities to the limit?

Maybe I’m wrong and there is a compelling reason for this…

Sorry. I may have misunderstood but I don’t see the difference between a thermal “via” and a TH Pad type in the Footprint Editor.

As I have read holes in thermal pad should be smaller then 0.3mm to avoid stealing paste during reflow soldering.

Just my few cents here:
Imho the TI recommendations for the MSP430, considering thermal relief, are a bit… exaggerated.
Like I have MSP430FR6989 in a lot of designs and due to some power lines below there are just 5-6 Vias (0,3mm) scattered randomly for thermal relief. Totally fine. No thermal issues under full load, even.
Like the max I was able to measure was ~2°K above ambient.

edit: Oh snap! Totally overlooked your package… I use the bigger one, since I need all the IOs.

The ti example board layout suggests 12 holes rather than 16 and has 9 equal solder paste apertures


I agree yet there is a difference in the DRC and the way constraints can be set for all holes & via vs those for uvias, if I could tell KiCad that my thermal vias were uvias they would use a different constraint.

Of course. To avoid stealing it’s necessary to reduce the paste pads apertures if the holes are setting to 0.3mm

The 9 holes seems more reasonable for a MSP430 package but I would do the same as LorenzG does. On the other hand, if the red-marked rectangles correspond to the paste pads, the stealing that Piotr has mentioned will occur.

I understand. Well I’m actually a bit neutral on this feature.

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The DRC is working as expected: you set a minimum hole size, and it checks against it. And JLCPCB (or any PCB manufacturer for that matter) won’t differentiate between vias connecting traces/planes and thermal vias, since it’s part of their manufacturing process.

I often have trouble when using some of the footprints with thermal vias when uploading the designs to Eurocircuits, because those footprints don’t comply with their minimum annular ring sizes. So I have to modify the footprints, which doesn’t change the outcome…