Custom Rules: Thermal Via in Pad

[Mineotopia]

I’m sure I’m not the first one to struggle with this but I searched the forum without any success.

Here’s the issue: The thermal vias in pads shipped with KiCad footprints have a hole diameter of 0.2mm. Many fab houses only produce 0.3mm an larger, except when it is a via in a pad where the positioning doesn’t have to be that exact.

I want to create a custom rule for that, but I’m not sure it is even possible.

Currently I have this:

(rule "thermal_via_inside_pad"
    (condition "A.Type == 'Pad'")
    (constraint hole_size(min 0.2mm))
)

However, this applies to all through-hole pads, not just those that are placed on top of an SMD pad. Is there a way to detect if a PTH is placed on top of an SMD pad?

[RaptorUK]

@Mineotopia

I’m sure I’m not the first one to struggle with this

Pretty sure this is along similar lines . . .

When is a via not a via?

The PCB I’m currently working on (a redesign to address issues) uses a ti MSP430 microcontroller on a ti package (drawing ref: RHA0040B) VQFN (40 pin), 6 mm × 6 mm body and 4.15 x 4.15 thermal pad. The specs for the footprint include thermal vias, with suggested 0.2mm holes. So I initially used the ti VQFN 40 pin footprint that is included with KiCad (Package_DFN_QFN:Texas_RHA0040B_VQFN-40-1EP_6x6mm_P0.5mm_EP4.15x4.15mm_ThermalVias ) but ended up modifying my own to match what was suggeste…

[Mineotopia]

thank you, seems like it. However, it does not solve my problem

[RaptorUK]

Nope it doesn’t, just wanted you to know you are not alone

[Mineotopia]

That being said, at least for JLC the described scenario is irrelevant. I’ve seen some fabs though where they stated something like this. Not sure which though