Forgive me for what may be completely obvious question
The project i am working on (my first) has 4 layers, i have signals on the top and bottom layer and have opted for a ground plane on layer 2 and using layer 3 for the 5V and 2.5 Power rails. I am assuming this is a sensible approach.
My question is, is this the best way to connect SMD components to each power plane in my attached image? Basically i have dropped a via wherever i need to connect to each plane. As this is a pretty large board i want to check this is correct before i have to undo hours of work of routing because i didnt understand what i was doing was wrong.
Brace yourself for the many varied opinions you will get, grounding an GND/power planes is potentially a complex and therefore give much scope for misunderstanding and huge variety of opinions. I know enough to know I don’t know enough . . .
One comment I would make, C2 as a decoupling capacitor should be between IC6 pin 8 and 5V so move the via to the other side of C2’s +5V pad.
Depends on the Project. How complex is the board? Do you actually need 4 layers?
I would place a decoupling capacitor for each power pin pair on every IC. This Capacitor is directly connected to the 2 power pins of the IC. In your case i would draw a track directly from IC6 Pin 4 to C2 Pin 1 without going to a different layer first. But that is just how i would do it, maybe some other people that may or may not know more than i do, would use a different approach.
Other than that, it is hard to say something without knowing your project. What components are placed? What are the frequencies? What buses do you use? Do you have Analog signals? If so, what requirements do you have there? …
I would place a decoupling capacitor for each power pin pair on every IC. This Capacitor is directly connected to the 2 power pins of the IC. In your case i would draw a track directly from IC6 Pin 4 to C2 Pin 1 without going to a different layer first. But that is just how i would do it, maybe some other people that may or may not know more than i do, would use a different approach.
Quite a large project for a beginner. Just be aware that the risk of doing something wrong is higher and the chances to be able to fix it by hand later can turn out to be very hard on a board with more than 2 layers. So make sure to check everything 3 times before production.
the whole point of having a capacitor as close as possible to the pads is to minimize the inductance of the connection between capacitor and IC power pins. while not wrong as it confines fluctuating return currents of the IC to the subcircuit, I usually would go for a direct via to the GND plane close to the GND pad instead. Like this the return path has a way lower inductance then with the narrow wire in the example above.
A problem here is that the IC has a bad power pin location, i.e. the power pins are not next to each other like it should be. You can’t create a very clean path for that.
Anyway, it probably doesn’t matter in practice for this IC. If it would, the power pins would be next to each other.
In theory, it can be different for different ICs, analog vs digital, … But again, it probably doesn’t make a measurable or noticeable difference in the end.
If you do two sided population it could be also an idea to move the cap to the bottom layer and place it right under the IC to equal the connections to the GND and power pad.
Be careful with your courtyards. IC6 apparently does not have a courtyard (and I’m guessing it is not a default KiCad footprint either) Putting the footprints too close together may make it difficult or impossible to do automated pick and place.
You can put the decoupling capacitors on the bottom as Tojan has shown, but it makes assembly more difficult. Assembly is easier if only one side of the PCB has footprints.
@Tojan Those footprints with rectangular pads look very old. Why are you using those? Are you still using the (ancient) KiCad version that came with those libraries?
To be pedantic, this way below has a shorter distance between pin and decuppling capacitor and the same distance between pin and GND-Plane. Probably the same story with the inductances.
The other question is where to put the via or if it is smarter to use more than 1 via.
A other approach is to use a GND plane on the top layer. I personally would switch between 5V and GND planes on the stack. meaning: Top: Use GND plane between the signal tracks, inner top: 5V plane without signal tracks or only very few signal tracks, inner bottom: GND plane without signal tracks or only very few signal tracks, bottom layer: 5V plane between the signal tracks. Or vice versa.
Then we wouldn’t have this discussion. One of both (either GND or +5V) is already present as a plane on the top layer and the other can be made as short as possible. Of course there should still be vias stitching the 2 GND and the 2 +5V layers.
@onemanonelaptop You see, not everyone agrees on how to do it best. I still think it doesn’t matter in the end. All approaches i saw in this thread should work, as far as i can tell.
What is it for a IC and what clock rates does it use? Does it have any analog functionalities?
Be careful with your courtyards. IC6 apparently does not have a courtyard (and I’m guessing it is not a default KiCad footprint either) Putting the footprints too close together may make it difficult or impossible to do automated pick and place.
@paulvdh its an 8-pin plastic SOP (225 mil) package according to the data sheet, ive got it marked down on my notes to find the exact correct footprint for it as im unsure about it, and its lacking a courtyard reduces my confidence levels in it. I would have though kicad would have had a default footprint but i didnt spot it.
Continuing to nitpick or split hairs (both terms from Google translator and not sure if mean what I wanted)…
Gnd at top has many big and long holes in it so it is not good return path for most of tracks. As all signals are related to GND then in my opinion at 4 layer PCB the first layer under the layer with ICs on it (here it is top layer) have to be GND. No exceptions.
For many years I was designing only 2 layer boards always with bottom being full GND.
It was possible because:
I frequently use 0603 47 ohm resistors at digital signal lines close to the source - in my opinion they reduce supply current pulses as changing state signal need only to reload its own output capacitance and reloading tracks and inputs of another ICs capacitance is little delayed. These resistors help me to untangle the connections,
I used microcontrollers in TQFP cases. At top I went with VCC under it and then propagated VCC starry going out through all corners and through all VCC pins,
I had nothiong against using some 0Rs to have my GND continuous.
I linked it few times but once more - here is PCB made according to these rules:
So when I moved to 4 layers the continuous GND laying under all signal tracks was my priority so if elements are at top then it is In1.
I was reading many times that In2 is typically used for VCC and other supply and was thinking that I will do it that way. But someone here at forum (year or two ago) said that he uses both inner layers for GND and I said: bingo - it will be the solution I will use. Thanks to it you need not to place blocking capacitor whenever you go with track from top to bottom (to allow return current to jump from VCC to GND or opposite). Via connecting both GND planes near the track jumping layers is replacement for this capacitor.
I am writing ‘will’ as till now I have designed only few 4 layer PCBs and all of them had In2 empty. Even the PCB manufacturer asked our contract manufacturer and he asked me if it is not a mistake, but it was as I wanted it (I needed as little GND as possible there but I had to use 4 layers because of QFN package that didn’t allow me for the trick with VCC under it.
Next I will take @paulvdh example to show how I would do it.
Placing the Vcc via to the left of pad 8 would also be a small “improvement”, because it reduces the loop area. But it’s clearly in the area where further optimizations are mostly not worth the effort.
It also depends a lot on the sort of circuit you are designing. Apparently it is some audio design with opamps, and it will therefore not have much high frequency content at all. Most opamps are not even capable of switching anything faster then a few MHz. Compare this with fast digital logic, which can have signal content up to several Giga Hertz. (Important: With digital stuff, it’s the switching speed and thus flank steepness that determines the frequency content, and not the switching frequency of the logic itself) even with audio opamps you should put the decoupling capacitors reasonably close to the IC’s. If your decoupling capacitors are too far, away, you may introduce phase shifts between when an opamp wants more current to do something, and when it gets that current, and this may lead to stability issues. But it is not as critical as with high speed logic. With audio frequency stuff, even a few cm may be ok.
Rick Hartley (from altium) has made a 2 hour video over GND planes and their effect on signal integrity and EMC behavior, and it is worth watching. Robert Feranec has also made a bunch of video’s on this topic.
I left GND connection between C and IC on both PCB sides thinking of getting as low impedance of connection as possible.
I have read that it is better to have IC gnd pin connected directly to C gnd pin and then to GND plane (like I connected VCC). Thanks to that, voltage drops made by currents flowing through GND planes being not added between C and IC gnd pins, and power current pulses of this IC are not inserted into GND plane.
So I preferred low impedance of connection over such signal reasons, but I am used to use digital ICs and here we have OpAmp so it is not taking such short and high current pulses from C so may be isolation of signals travelling through GND plane from our supply blocking circuit should be preferred over low impedance.
An a little more nitpicking . . . which, in this case, is probably off topic, try and avoid acute angles as this can lead to over etching . . . make your tracks a little wider and either bring them off the pad at the pad corner or at the pad flat areas.
Let me add my thoughts, too.
First I would like to mention how currents flow. If you have an L-shaped track for the signal and a GND-Plane for the return, think of DC and the current will mostly flow the direct way from one end of the L back to the other (diagonally). Current will take the way of least resistance.
But if you have AC, it will no longer take the way of least resistance but the way of least impedance.
So, what determines the impedance. The higher the frequency, the bigger is the role of the inductance of this Loop.
The inductance of a loop rises with the length of the track, it drops with wider tracks and it rises with the loop area!
The current cannot change length or width but on the GND-plane it can chose a way with smaller loop area!
So with rising frequency the return current path will move more and more under the track. Finally, the area will swing from horizontal to vertical, i.e. the area will mostly reduce to the distance between the track and the GND-plane.
For the optimal design, this means:
The GND-Plane must be the first layer below the component layer.
The smallest area is by using a ‘L’ for the +5V and a mirrored ‘L’ for GND (only 90 deg and no diagonals). You can even pinch the tracks closer together than the capacitor pins.
The capacitor has to be as close as possible to the IC.
The vias to the planes are connected by separate tracks to the capacitor and not to the IC or somewhere in between.
The tracks should be made wider (at least the with of the IC pads)
