Hi,
I’ve been able to easily create copper heatsink for electrically connected pads of smt components, using the fill zone tool and associating the filled zone to the appropriate electrical net name.
However, I’m a bit lost on how to procede in the case I want to connect a copper heatsink on the pad 4 of a Package_TO_SOT_SMD:SOT-223 that have, by default, no electrical role, hence no electrical connection.
For that package, in fact, the pad number 4 is there just for its thermal and mechanical utility.
Nevertheless, if I try to create a fill zone around that pad, I end up, despite all the options I choose (Fill zone, no THT nor Thermal relief), with having that unwanted clearance evidenced by the yellow line in the image below
What’s wrong with my approach? I’ve also tought to manually adjust the pad dimension changing its properties, still, this doesn’t sound as the “formally corrected” approach to me. Any help please?
Normally one uses a pad defined in the footprint instead of using zones. At least in the area under the component. (But the pad can be larger. In that case make a separate pad for defining the soldermask cutout as you probably do not wish to have exposed copper outside the area not covered by the component)
If you then want to connect to an even larger zone that fills the area around the component where no other traces are then you need to have this pad connected to a symbol pin. (add a pad number and include a pin in the symbol with the same number. You can give that pin the electrical type not connected. You can still connect a local label to that pin to make finding the correct net for the zone easier. At least i hope that a label connected in such a manner will create a net with its name even if there is no other pad that connects to that pad. I could be wrong about that.)
Uhmm…I’m not sure I’ve understood correctly all you wrote but it seems to involve working on a “custom” footprint modification and, in my humble opinion, it seems a bit too much work for such a “common” operation in the pcb world. Is it really the only way? What about the other approach I tought about, modifiying directly the pad properties?
Or, as an alternative, what if I “force” the assignment of a net name to the pad number 4? I mean, joining it to one the remaining three pads of the footprint (pad 1 or pad 2 or pad 3, i suppose its the same…) and then I proced with the “standard” fill zone approach?
The common way is to have the symbol fit the footprint such that all footprint pads can be connected on the schematic side. (Even pads that are not electrically connected to anything.)
Doing this will allow you do connect a copper zone to this pad. Set it up to have solid pad connection and you can increase the pad area without needing to changing the footprint.
Possible but reduces the maintainability of your project.
Do you want that pad to be electrically connected to one of these pins? Is it a good idea to have a large floating antenna connected to them?
Double (and triple) check your datasheet. Often that pin 4 (also sometimes called tab as a historical reference to TO-220 style packages) is electrically connected to one of the other pins. If so, you don’t want to have a 2/3 chance of shorting your circuit out there by chance. (Think of Last Crusade when the antagonists “chose poorly”…)
EDIT: OK, never mind. You have already aware of internal connections on these SOT223 packages and have checked the datasheet. Move along, nothing to see here.
Ok, I got it; Still, it requires creating a symbol; wherever possible, I would prefer for a less laborious way than this one; when other alternatives will be out of reach, I’ll consider this as the road to follow, thanks
I got it; I’ll avoid this approach.
Uhmmm…let me disagree on this one: look at the specs of the npn I’ve choosen for the project:
It has the pad number 4 internally connected to the pad number 2 (npn collector), hence it seems I chose the wrong footprint for this component right from the start: I’l change it from Package_TO_SOT_SMD:SOT-223 to Package_TO_SOT_SMD:SOT-223-3_TabPin2, solving simply my problem.
On the other hand, if what you said about the “large antenna floating” would be true, this would mean that the the manufacturer of this npn transistor, and in general every other manufacturer adopting the SOT-223-3_TabPin2 for their parts, would be building unintended antennas, and I doubt that’s true :-); Maybe I was not clear exposing my idea? Don’t know
Sure, for my specific case, it was my fault in assigning the wrong footprint, you’re right, I’m sorry
Nevertheless, I’ll surely encounter in the future some parts having the SOT-223 footprint, the one with the Pad number 4 not electrically connected, and in that case my doubts would be the ones I tried to dissolve asking here on the forum.
Hence, if a day I’ll find myself in this latter case, considering my previous observations, do you still think that joining the pad number 4 to another pad (for example the pad number 2) would be a bad approach?
Every pad that you want to connect to anything even if it is an isolated copper zone needs a pin in the schematic. So yes if you ever have a component with some pin only used as thermal or mechanical connection you will need to assign a pin number to it in the footprint and have it as a separate pin in the schematic symbol.
It is very rare for the tab (pin 4) to be isolated. The SOT-223 package is used to at the 1-2W power level and works by having a relatively low thermal resistance from the die to the PCB copper. If the tab was isolated, the package would be no better than a SOT-23
Again, I state my opinion that a Tab is not a separate mechanical Pin; even if a couple of manufacturers now present them as such on DataSheets (it is still not yet the industry normal).
@Gaetano_Cirillo In the DataSheet you overlooked the fact that Pins numbered “2” and “4” were electrically connected as shown on page 2 of the schematic link you provided.
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For others still reading…
It just did not occur to me that some users would prefer to just keep adding more Footprint Pad Numbers to existing connections; all on the same net.
What if the schematic Symbol only needs 4 connections to each separate net, but the physical part has nine Pin/Tabs and the body as GND?
GND
NetList # 1
NetLIst # 2
NetList # 3
In my opinion, this conflation of Symbol nets and Pin names needs to be made more clear for all users.
I think this one has been overcomplicated (probably because I’ve misinterpreted it ). In mind it’s not at all uncommon to have a pad or tab that is only thermal, not electrical.
Invariably, the symbol shows this as a pin, with a nonsensical number (usually 0 or one more than the actual pin count). You simply put a “no-connect” flag on it.
Thus in the footprint you have what the software assumes is an electrical pad that you’re free to connect to pours/floods or even vias to other planes.
I’ve attached an example of where I’ve done it recently with an MSOP.
Those pads are often electrically connected to one of the other pins or to the substrate of the chip inside, and most often it is stated in the datasheet to to handle those pads.
Why put a no connect in the schematic, with text what to do with it.
Why not simply put a wire on it with the label “Thermal_plane”?
That would create a net with a single pin and (very likely) show up in the netlist with that name, so you can create a zone with that name and it will connect.
Edit:
According to datasheet of DS600:
PAD. Connect to GND or float. DO NOT CONNECT TO SUPPLY. The exposed pad is the best way to conduct temperature into the package. Connecting PAD to a ground plane can assist in properly measuring the temperature of the circuit board.
Turn it around:
If you do not connect PAD to GND it is likely to pick up noise and lower the temperature measurement accuracy.
And there are more references to “PAD” in that datasheet, I haven’t read them all.
I’m kind of neutral on the point but I am curious about your objection to having a pin for every connectable “lead / pad / etc”
I realize the use of a Arduino Pro Mini board on a PCB is very hobby related, however as an example there are a number of grounds, however I want to define in the schematic which grounds are connected to certain parts of the circuit.
I am of the general opinion that the symbol should remove as many points of failure as possible.
If the manufacturer defines that all these ground pins need to be well connected to system ground (for example for EMC reasons) then i suggest to stack these pins such that the user can not try and use the component as a ground bridge.
This should explain why we over at the official library have the policy to stack ground pins in nearly all cases (There are exceptions but there really must be a good reason given in the datasheet or any other design document.)
It is a bit different for positive supply pins as one will want to be able to define which of these gets which decoupling cap. (Datasheets mostly state that decoupling caps of a given value need to be near specific positive supply pins.)
It really comes down to enhancing the understanding of the device.
I expect that (for most parts) every pin is a separate signal, and that the tab is a joint connection to a pin. It is also expected that the tab will be the thermal connection for the device.
And, mostly, because the tab does not even look like the other pins. So this begs the question, from a design standpoint, “Is the tab a tab, or pin style two?”; because it most certainly can not be soldered to the board with the same PCB pad dimensions as the other pins.
This concept of a tab being a pin would also clutters up the schematic in KiCad. The concept forces the schematic to have 4 pins for most higher current transistor and linear regulator devices. This goes against the very basic concept of conveying the schematics intent to the user in the most readable presentation as possible.
The concept of a tab being separate from a pin is also useful in KiCad during the design. I caught a design error in PcbNew because I knew that a Footprint had a tab tied to a certain pin. Having the tab be a tab, tied to a pin, makes it easy to see which pin the tab is tied to in PcbNew; as it has the same pin number on the pad.
Hope this helped convey my resistance to the borg… er, new trend in the industry by a few manufactures.
I respectfully disagree. A schematic is a product drawing that documents the electrical portion of a design. While it is a poor document if it is difficult to follow, easy to follow is not the primary goal.
I came from an environment where the designer (circuit,not PCB) needed to understand every pin function and tab function etc. Championing aggregation of some features is in my opinion playing to the lowest common denominator.
What would you propose for the LM1877? Would you use 9 pin numbers or 14?
Hope this helped convey my resistance to the borg… er, new trend in the industry by a few manufactures.
Funny, I’m not driven by any industry nor mfg. I am unaware of any new trend in this area. On the contrary, I find the industry has not settled on such common things like pin numbers vs pin functions etc.
I enjoy reading opinions different than mine, that is how we all learn
I did not look at the device but i can tell you that the kicad way of doing things is that the footprint does not care for which part it is used. You always use generic pin numberings (So i would guess 14 different pad numbers assuming your part has 14 leads)
This allows you to use one footprint to represent every part that comes in the generic SOIC-14 package.
The symbol however can be made such that multiple pins are stacked on top of each other. For some pins this really is the only sensible option. (Stacking means pins placed on top of each other and only one of them is visible. Other programs have the option to map one symbol pin directly to multiple footprint pads. Stacking is the workaround used for getting this feature in kicad.)
Any output pin that as two leads intended to be connected on the board is an example. As having two of them would give you a false positive in the ERC when you then need to connect them in the schematic. Having one of them randomly as passive without stacking will make ERC a lot less useful as well as it now does not really check if you connected that one wrongly to another output. So the only real option that gives you the chance to have a generic footprint and still use ERC to its fullest is to stack these pins.
I agree the 14 pin (dip or SOIC) with 14 pin numbers is the right way to define the footprint.
However I would prefer to not stack the pins for the schematic symbol. I guess I don’t have enough confidence that the program will ripple the connections requirements through to the board. This has nothing to do with Kicad, I don’t accept such design automation from any program, I want to see all the pin connections addressed on the schematic.
Going to @Sprig 's clarity of schematic statement. I feel with stacked pins someone picking up the design some time later might miss the connection of pins combined into one pin number.
But that’s just me.
The great point is with Kicad we both get to document the design the way we see fit
