Copper Heatsink on not electrically connected pad


Well i for one prefer powerful checking tools over human checks as i do not trust humans in general (including myself)

This is why i stack pins with the knowledge that stacked pins are connected. (Their connection point is on top of each other -> the very definition of a connection in kicad.)

And as i described: Not stacking pins can easily remove some of the power from the electrical rule checker -> simply not worth the tradeoff. You gain the option to have a schematic checked by an unreliable (and inconsistent) being but loose the chance to have it done by an algorithm that is reliable in a well documented way.

It would however be nice to have some indication that a pin represents more than one pad. (Maybe even indicate the number of pads it represents. Plus some way to discover which ones.)



When you say “powerful checking tools” I assume you are referring to the ERC when pins are labeled Power in, inout, etc. To be honest I’ve not delved into the Pin configuration yet as my circuits have been relatively simple. So you likely have a point there. Although I’m not sure how having multiple pins would be handled in by ERC.

Lets assume we are part of a small company with some new ideas that may get patented or perhaps just become a production item. Not everyone will be viewing the schematic in Kicad. It will most likely be in pdf form. In this case stacked pins could be misleading. I suppose one could add a note to the schematic but I would think that would be going backward.



In this particular case, I’d probably just show all of the GND pins on the symbol. Keep in mind, that my main point above was that pins(leads) and tabs can not share the same Footprint pad; and it is common for the tab to physically share the same function as one of the other pins(leads).

This link describes the typical way that through hole parts were described when they also had a mounting tab:
TO-220 Wiki
To me, there does not seem to be any good reason to deviate from this generally accepted standard just because a manufacture now makes the same device in an SMD package.

There is a particularly weird part I have in a design. The package has eight(8) SMD gull wing leads and five(5) of them are to have no connection.

This is the symbol that I created for this part.

Now that I think about it, for the LM1877, following my example above, it would make sense to have 2 GND pins visible, with pins three(3) and twelve(12) shown as GND on the symbol and the other pins stacked on top of those pins.

As the part has 14 leads, and pin 14 is listed on the symbol as Vcc, it can be extrapolated that the missing pins on the symbol must be the other GND pins.


Most people viewing your schematic really don’t care about such details. They want to see the overall function of the system. This is communicated by having a single visible pin. (No reason to include too much detail here)

By the way the using stacked pins workflow that i prefer makes an important assumption. The assumption is that the symbol is trustworthy. Meaning instead of reviewing this detail when making the schematic you review it in detail when creating (or downloading) the symbol.

This means you move part of the review to a different stage. So if you want somebody external to check your schematic including pin assignments you would need to send over the schematic and the symbol (The symbol with the pin table visible.)

You could even have two different groups of people for these tasks (reviewing a schematic requires a vastly different skillset compared to reviewing if a symbol matches the datasheet. The later requires somebody patient that can read datasheets well. The former requires a well trained engineer.)


For thermal purposes, not necessarily electrical. The difference is that not connecting them electrically is okay, unlike ground pins for example. In some cases (eg. temperature measurement, bonding to heatsinks, etc.) that matters.

Okay. What should I label the wire connected to the pad of the other temperature sensor on the board which is to be thermally bonded to a particular heat generating region of the board? Connect_to_the_electrically_isolated_thermal_plane_under_the_hot_region_but_not_near_the_thermal_plane_of_U4? Seems a little cumbersome and at odds with the documentation convention established so far…

What is my temperature accuracy spec? Is accuracy more important than measuring the right thing? What about ensuring that the ground plane temperature does not significantly influence the temperature of the device under test? Should I recall these products from the field, which have undergone and passed significant environmental testing despite not connecting PAD to GND? I’m being sarcastic of course, I lack the ability to express my confusion with your advice, which seems to be largely about solving problems that don’t exist.


Great to understand the rational behind this, which I found confusing when I came across it. I can’t say I’ve ever looked at a schematic containing an IC for more than a few seconds without wanting to know what’s connected to each pin. So our schematics that use symbols created according to this convention look like this:

The notes help review and board testing. Now I know the rational it helps, but I think we’ll continue to add the notes for those that aren’t aware.


I guess it comes down to what you are used to and how you learned. In my experience working for a number of electronic product mfg, the details are important. Perhaps in the hobby world that may not be the case.



My dislike of stacked pins is that there is no graphics clue that you are looking at a stack. I have wasted time before looking for a pin hiding in plain sight in a stack.

Why can’t we have a special pin graphic style to indicate stacking?


I tend to agree with @Rene_Poschl on this subject matter. All the extra fiddily stuff just is not needed on most schematics most of the time.

That is a good idea!